CPU Architecture - GROUP
Data Flow of CPU and low level blocks - GROUP
Instruction Set - GROUP
Defined the Finite State Machine - GROUP (revised by Karey Tsang)
System Timing - GROUP
Designed and Tested the PLA and registers- Karey Tsang
Designed and Tested the PC and bus controllers - Michael Warner
Designed and Tested the ALU - Christine Pan
Layout of Chip - GROUP
Routed the BOMB! - Christine Pan
Tested and Attempted Debugging of the BOMB! - GROUP
Layout of Final ALU (The BOMB! -- Part II) - Christine Pan
Routed the Final ALU (The BOMB! -- Part II) - Christine Pan
Tested and Debugged the Final ALU (The BOMB! -- Part II) - Karey Tsang and Christine
Pan
Analysis of Longest Path - Karey Tsang
Analysis of Maximum Clock Frequency - Michael Warner
Web Page Design & Organization - Christine Pan