JAWs Algorithm Schedule
Submitted 22 September 1998
Instructions: 8-bit fixed length instructions
Registers: 4 4-bit general purpose registers, a 4-bit memory access register,
an 8-bit program counter (PC)
Store instructions in Instruction Memory (IM)
Initialize PC and all regs at power up
Fetch instruction at PC
Decode instruction - break instruction into
- Inst[7-4] - opcode
- Inst[3-2] - regds
- Inst[1-0] - regs
- Inst[3-0] - immediate
From the opcode, generate control signals.
BEZ
Compare rds to 0. If taken: concatenate rs amd rm. Feed this
into the PCSrc MUX.
BGZ
Compare rds to 0. If taken: concatenate rs amd rm. Feed this
into the PCSrc MUX.
SLL
Pad rds with 00. Assert ALUSrc2
ADD
no control signals asserted
SUB
no control signals asserted
NOT
no control signals asserted
AND
no control signals asserted
OR
no control signals asserted
LW
Concatenate rs and rm to get memory address. Assert MemRead.
Assert RegWrite
SW
Concatenate rs and rm to get memory address. Assert MemWrite.
SETM
ADDI
Assert impreg3. Assert 4imm. Assert ALUSrc2. Assert RegWrite.
LDI
Assert impreg3. Assert immdata. Assert RegWrite.