Project Description - JAWs CPU

27 October 1998

Overview

We plan to build a 4-bit CPU. Instructions will be 8 bits long, with a 4-bit opcode. The on-board ALU will use a 3-bit opcode.

We will use off-chip memory for data and instruction storage, with space for 256 8-bit words for each. On the chip, we will have 4 general purpose 4-bit registers, and one special memory address register, which (when addressed by a special instruction) contains 4 bits of a memory element to be accessed.

Circuit Layout

The following elements will be necessary components of our CPU. See the logic diagram for more information regarding the implememtation of these elements.

Latches - 4- and 8-bit as shown in logic diagram

Multiplexers - two 1-, one 2-, four 4- and two 8-bit input multiplexars

Registers -

Our register file will consist of 4 4-bit general purpose registers. Each storage cell will be implemented as a 2 read port/1 write port SRAM cell. Decoding for the read and write lines will be performed by 3 2-to-4 decoders.

For memory access instructions, we will use one 4-bit memory access register.

Add-one unit -

To increment our PC, we will need to add 1 to an 8-bit number. We plan to build a customized adder for this (rather than, say, use our ALU).

The adder will be comprised of 8 add blocks, each with 2 inputs: carry in and the input bit, and with 2 outputs: the sum bit and a carry out bit. The first block will have a carry in of 1; subsequent blocks depend on the carry out of the previous block.

The following logic operations will be performed in each add block:

    OUT = (IN XOR CIN)

    COUT = (IN * CIN) = (IN' + CIN')'

We will use the compound logic XOR, as described in class, for OUT; we will use a NOR on the inverted inputs for COUT.

Zero Logic -

For our branch detection, we will need to know whether the 4-bit two's complement number supplied by the register file is equal to zero, and also whether it is greater than zero. Assume the number is DCBA, with D as the MSB.

For the equals zero logic, we simply need to NOR all of the bits, as all bits must be zero:

    EQZ = (D+C+B+A)'

which requires a 4-input NOR gate.

For the greater than zero logic, we must analyze the sign bit and OR the rest of the bits:

    GTZ = D' * (C+B+A)

This simplifies to:

    GTZ = ( D + (C+B+A)' )'

which uses a 2-input NOR gate and a 3-input NOR gate.

ALU -

ADD - 4-bit Manchester adder
Our adder will take advantage of carry-lookahead techniques to increase speed. The basic idea behind carry-lookahead adders is that you define a generate and a propagate signal for the ith bit adder cell. The generate and propagate signals are only dependent on the ith bit values for the operands A and B. The generate signal produces a one when a carry out is definetely going to be asserted. The propagate signal produces a one when the ith bit values for A and B are such that they would "propagate" a carry when the bit adder cell received a carry in.

    Gi = Ai & Bi

    Pi = Ai + Bi or Ai (+) Bi (since the generate covers Ai & Bi)

This leads to

    Ci+1 = Gi + (Pi & Ci).

This definition of the generate and propagate signal leads to the fact that the generation of all carry bits can be accomplished in two levels of logic. This follows from the sum of products which arises from the recursive relation of the carry bits given above.

The sum for each bit adder cell can then be written as

    Si = Ci-1 (+) Ai (+) Bi.

The Manchester Adder physically distributes the carry signals perpendicular to the data flow from the operands to the sum.

SUB - invert the bits of the second operand, set the carry in for the adder to 1.

NOT - use 4 inverters (one per bit)

AND - use a NAND gate followed by inverter for each bit (total of 4 and 4)

OR - use a NOR gate followed by an inverter for each bit (total of 4 and 4)

SLL - use a 2-4 decoder with our previously designed barrel shifter. Literal<2-0> will be zeros. High bits will the the value from the register. We will need to reverse the order of our shift controls.

Changes Made:

27 October 1998
Changed logic used for add-one unit. Now, COUT=(IN' + CIN')', instead of COUT=(IN*CIN).

20 October 1998

Register descriptions and Manchester explanation added.

13 October 1998

Initial project description moved to link below. Zero-logic cells and add-one unit detailed.

15 September 1998

Original project description submitted.