Since our instruction take varying amounts of clocks to complete, we have performed our timing analysis on a per instruction basis. Our timing discipline then allows us to have valid timing for instruction after instruction as long as we make sure that each instruction's timing will not effect a following instruction's timing.
The timing of the instructions can be broken up into groups of instructions which have common timing and data paths. The groupings of signals primarily serve for clarity in the diagrams. Certain signals controlling a particular datapath may not be labelled; however, the context of the instruction or grouping should make the situation clear. Also, some latches are labelled with signals which are stable over several clock periods. The state diagram is very helpful to look at when trying to make sense of the stable periods.
| Timing Group | Instructions in Group |
| ALU | ADD, ADDI, SUB, AND, NOT, OR, SLL |
| Branch | BGZ, BEZ |
| Load | LW |
| Load Immediate | LDI |
| Store | SW |
| Set MemReg | SETM, SETMI |
| Zero Register | ZERO |
| No Operation | NOP |
13 November 1998