REQUEST: REPORT
ID: 58764
P-NAME: gsat
Fab-ID: T01SDK
P-P: /* I have on file the project password */
REPORT:

The GSAT chip solves logic satisfiability problems. Given a Boolean expression
(in a specific but general canonical form called 3CNF), the chip uses a
randomized algorithm (GSAT) to find a truth assignment to the variables which
satisfies the expression. The expression is kept in 4kB of off-chip SRAM, and
the work variables (128) are kept in on-chip register space.

Due to logic design flaws (detailed in the full report at the URL below), none
of the chips are fully functional. However, the behavior of each the 5 samples
was identical.

The on-chip register file was tested extensively because it was directly
readable and writeable from the pins. We also had a number of other long test
vectors, which together test each branch and case in the GSAT algorithm. Due
to the above mentioned design flaws, the controller wrongly declares success
after just one iteration (which is several hundred cycles), so there is no
opportunity to test the later branches.

The chip failed completely when clocked above 2.5 MHz. It is not known what
components were the first to fail.

URL: http://www.owlnet.rice.edu/~tdanner/gsat-testing/

SUBMITTED BY:
Tim Danner
tdanner@rice.edu

Reuven Lax
rlax@rice.edu

Andy MacKay
mackay@rice.edu

REQUEST: END