REQUEST: REPORT
ID: 59678
P-NAME: nsekila
FAB-IB: T01SDH
P-P:
REPORT:
This chip implements a noise cancellation filter using a well-known adaptive DSP algorithm called Least Mean Square (LMS). The chip takes as inputs an 8-bit noisy signal as well as an 8-bit noise reference signal and produces an 8-bit filtered output. The filter implemented is an FIR filter with 8 taps that are stored in a stack of latches and the filtering is performed using 8-bit signed multiplication and 12-bit signed addition in a process that takes approximately 180 clock cycles per iteration.
The chips arrived in good condition without any damage and there were no problems with the packaging. Four out of the five chips were fully functional. The fifth chip was incorrectly connected to power and ground and we destroyed some of the inputs so we were unable to determine if it worked before we destroyed it.
We used a set of four test vector inputs that test the chip for four iterations on varying inputs for X and the desired signal. Since our chip is adaptive, each test depends on the previous test because the Weight values are updated and a new X input value is loaded on each iteration. The inputs we used were the same test case that we used last semester in IRSIM to validate the functionality of the chip. In addition to viewing the final signal output, we also are able to view some intermediate signals through our debugging pins.
We ran the same test vector inputs as the aforementioned tests in order to determine the maximum speed at which the chip functions. Using a non-overlapping two-phase clock, our chip still functions correctly (goes through all the correct states and obtains the intermediate and final outputs we expect) at the maximum rate possible with OMNILAB, 8.5 MHz (34MHz sampling rate).
URL: http://www.ece.rice.edu/~dodeedo/elec422/
SUBMITTED BY:
Yonghui Cheng, chengyh@rice.edu
Damian Dobric, dodeedo@rice.edu
Ping Tao, ptao@rice.edu
Shunxi Wang, shunxi@rice.edu
REQUEST: END