Group Y

Yonghui Cheng

Damian Dobric

Ping Tao

Problem Statement

You are working in a computer lab with 50 machines blowing air like crazy in your ear. After a couple hours of this you decide you are going to go crazy if you don’t get away from this noise. You put on your headphones to listen to some music from your PC, and this helps a little but you still can’t escape the noise. The idea of this project is to implement a noise cancellation filter unit that resides between your headphones and the music source to eliminate as much of the background noise as possible and allow you to enjoy your music without getting a headache.

System Overview

The diagram below depicts a general adaptive system. The purpose is to filter the input signal so that it resembles the desired signal input. The input signal is filtered to obtain the output signal. The error signal is obtained by calculating the difference between the desired signal and the output signal. This difference is fed back into the adaptive process that evaluates the similarity between the two signals and, according to some performance criterion, modifies the filter’s frequency response to increase the similarity. In our system, the adaptive process we are using is the LMS (Least Mean Square) algorithm and the filter we are using is the N-tap FIR (Finite Impulse Response) filter because of its simplicity and stability.

_xk – Input signal

d_k – Desired signal

y_k Output signal

e_k – Error signal

FILTER – Finite Impulse Response Filer (FIR)

Adaptive Process – LMS (Least Mean Square) Algorithm

Figure 1. General Adaptive System

VLSI System Components

FIR Filter

Figure 2 below depicts the process of the FIR filter. This filter consists of N-1 delayers, N multipliers, each with its correspondant weight, and N-1 adders. In our project we will have to share one multiplier and one global adder because of space constraints on our chip. N is the finite duration of the filter, or the number of taps, and the weights are the values of the N samples of the impulse response. The values of these weights determine the frequency response of the filter.

We will require an 8-bit word length for this project in order to achieve an acceptable sound quality. The filter will be implemented using N = 8 and we will need eight 8-bit shift registers for the input data, an 8-bit x 8-bit multiplier that will be used for all multiplication, and eight 8-bit registers for holding the weight values.

Figure 2. FIR Filter

Adaptive Process (LMS Algorithm)

The Least Mean Square (LMS) algorithm is an adaptive algorithm that is based on optimizing the mean square value of the error signal in the adaptive system shown in Figure 1. This can be achieved by adjusting the values of the weights of the FIR filter shown in Figure 2. The LMS algorithm is an approximation of the “Steepest Decent Method”, and estimates the gradient rather than obtaining the actual value of the gradient, simplifying the calculations to be performed and allowing the algorithm to be used in real-time applications. The resulting algorithm is the Widrow-Hoff LMS Algorithm, shown below.

W_k+1 = W_k + u * e_k * X_k

Wk is a vector containing the weights of the FIR filter, u is the step size, which determines the speed of convergence and stability of the algorithm, ek is the error, and Xk is the input vector. This equation reduces the calculation to N add-products.

We will require a second 8-bit multiplier in order to perform the multiplication in the LMS algorithm, and an 8-bit adder to perform the addition.

Other Information

Further details on the method of multiplication and the number of transistors required will be provided, but we believe that we can implement these components within the space provided within the limit of 5,000 transistors.

We have a preliminary idea for cascading multiple chips together by connecting the delayers in the FIR filters together while the multiplication on the chips runs in parallel and the final addition adds all of the results from both chips to calculate the error. Currently we are not sure about the performance of such a system and have to determine the delay involved in adding the results from both chips and in the feedback loop.