This chip implements a noise cancellation filter using a well-known adaptive DSP algorithm called Least Mean Square (LMS). The chip takes as inputs an 8-bit noisy signal as well as an 8-bit noise reference signal and produces an 8-bit filtered output. The filter implemented is an FIR filter with 8 taps that are stored in a stack of latches and the filtering is performed using 8-bit signed multiplication and 12-bit signed addition in a process that takes approximately 180 clock cycles per iteration.
Official Project Name: NSEKILA