HSPICE Analysis of Basic Cells
| Name of Cell / Block | Rise Time (ns) | Fall Time (ns) | Spice Plot |
| Inverter | 0.7 | 0.5 |
|
| NOR | 1.4 | 0.5 |  |
| XOR | 2.4 | 2.2 | |
| NAND2 | 0.9 | 0.8 | |
| NAND3 | 0.7 | 1.8 | |
| NAND4 | 0.6 | 2.6 | |
| NAND5 | 1.3 | 2.7 | |
| Latch | 1.6 | 1.6 | |
| Clearable Latch | 3.1 | 1.6 | |
| 2x1 MUX Subcell | 0.7 | 0.4 | |
The longest path in our circuit is from the output latches of the multiplier through the 12-bit adder to the input of the error output latch. We allow one clock cycle for the 12-bit adder to complete a computation, thus the adder is the critical circuit that defines the clock cycle time. We used HSPICE to analyze the worst case performance of the adder for both rise time and fall time. The worst case delay for both rise and fall time is when all of the outputs change from 0 to 1 and 1 to 0, respectively.
Rise Time
To determine the worst case rise time for the adder we simulated it in HSPICE with A0 - A11 = 1 and B1 - B11 = 0 while the LSB of B changed from 1 to 0, causing a ripple effect such that the sum outputs and the final carry output (S12 below) change from 0 to 1. From this simulation, the worst case rise time is approximately 26 ns.
Fall Time
To determine the worst case fall time for the adder we simulated it in HSPICE with the A0 - A11 = 1 and B1 - B11 = 0 while the LSB of B changed from 0 to 1, causing a ripple effect such that the sum outputs and the final carry output (S12 below) change from 1 to 0. From this simulation, the worst case fall time is approximately 23 ns.
We notice that the rise time is the larger delay of 26ns, thus our chip can run at a theoretical maximum frequency of 38.5 MHz. This is much higher than is even required by our chip, since f it runs at only several MHz it will still function properly because it only has to match the sampling rate of our A/D converters, which only has to be at least 4KHz. Since the speed of the I/O Pads is limited to approximately 25 MHz, our maximum operating frequency is 25 MHz.