Design Work
We have designed and fully implemented an adaptive noise cancellation filter at the transistor level. We have thoroughly tested our chip through more than 8 iterations of 200 clock cycles each and believe that it is fully functional, including the adaptive updating of weights. The HSPICE performance analysis we conducted indicates a theoretical maximum frequency of 38.5 MHz, which more than meets our requirements, while we know that the I/O Pads will limit us to approximately 25 MHz.
Improvements
Our current design implements an 8 tap FIR filter. This is an extremely low number of taps considering the average filter has at least 60 taps. If we had more space on our chip we would like to increase the number of taps to achieve greater accuracy. A second improvement to our chip could be to allow for cascading of multiple filters. Originally we wanted to implement this but determined that it would require sharing of almost all of the I/O pins and greater PLA controller complexity so we decided against it. If we had more time and space cascading could have allowed for increasing the number of filter taps by using multiple chips.
Comments on CAD Tools
We found the CAD Tools to be sufficient for our needs. One thing that we noticed was that the tools were designed for different models and thus IRSIM and HSPICE had extremely different results in terms of delay time. The current inoperability of CRYSTAL makes it difficult for us to comment about it. In addition, IRSIM was limited in its use of test vectors. For our project we had to simulate a large number of clock cycles, and IRSIM required us to create a bunch of separate command files because each command file is limited to simulating a small number of clock cycles.
50 Word Description
This chip implements a noise cancellation filter using a well-known adaptive DSP algorithm called Least Mean Square (LMS). The chip takes as inputs an 8-bit noisy signal as well as an 8-bit noise reference signal and produces an 8-bit filtered output. The filter implemented is an FIR filter with 8 taps that are stored in a stack of latches and the filtering is performed using 8-bit signed multiplication and 12-bit signed addition in a process that takes approximately 160 clock cycles per iteration.
Official Project Name: NSEKILA
|
Description of Task |
People Working on Task |
| High Level/Functional Design | YC, DD, PT |
| MatLab Simulations of LMS Algorithm | YC |
| System Level Timing | PT |
| Leaf Cells | YC, DD, SW |
| Counters | DD |
| PLA & PLA Simulation | DD |
| 4-bit Adder (Design, Layout, Simulation) | DD |
| 12-bit Adder (Connecting three 4-bit adders together!, Simulation) | SW |
| Rotate Stack (Design, Layout, Simulation) | PT |
| 9-bit Multiplier Design | YC, DD |
| 9-bit Multiplier Layout & Simulation | YC |
| System Integration, Routing, Layout of Core | DD, PT |
| C-Programs for Testing Chip (for generating test vectors and running IRSIM extensively) | YC |
| Chip Debugging | YC, DD, PT |
| I/O Pad Routing | PT |
| Leaf Cell and Adder SPICE Analysis | DD |
| Performance Analysis | DD |
| Project Presentation | DD |
| Web Page Design & Content (Including Final Report) | DD |
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4. B. Farhang-Boroujeny, Adaptive Filters: Theory and Applications. John Wiley & Sons Ltd, 1998.
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