The PISCES is a line-drawing chip. It will store endpoints of a line, then plot points between the endpoints using a Bresenman algorithm. It will also be capable of translating the line within the field.
Feature Set:
Overview
The device will allow the creation and rendering of line segments of various shades.
These line segments are internally represented by and manipulated as a pair of endpoints associated with a shade value and some state data. These "objects" are stored in a small bank of onchip RAM. From this bank, the objects can be individually loaded into registers, manipulated, and stored back to RAM. Possible manipulations include translation in any cardinal direction. All manipulations are performed on a single object within the scene.
After the line has been adequately manipulated with the transforms provided, a draw command can be issued to render the line. At this point, the line-drawing unit iterates through its image field, which is a bitmap stored in external RAM, and sets all values to 0 (the darkest value, and the background color). Once the field has been blanked, the drawing unit uses a Bresenman line-drawing algorithm to draw the line in the bitmap in external memory. This bitmapped scene is the final output of the device, which could be used to drive the image of a monitor, were such hardware to be added.
Functional Units
The main functional units of the device will be its instruction decoder and controller, the registers, and the linedraw subunit.
The instruction decoder will accept the input instructions and load/store register values, as well as operate the basic logic unit which will implement our provided transforms. This will also effectively control the entire device, except when the unit is in line-draw mode.
The onboard memory will be composed of cells of five 8-bit words. Each cell specifies precisely one object in the scene. The memory will be cell addressable, and only modifiable through load/store to the register cell. Thus, no value in the onboard memory can be directly manipulated. That cell must first be loaded into the register cell, its data operated on there, and then the cell must be written back.
The linedraw subunit will implement a Bresenman algorithm. It will be the only portion of the device to write values to the bitmap stored in the external memory.
In reality, both the instruction decoder and the linedraw subunit are part of the same finite state machine controller.
Algorithms
As stated earlier, the Bresenman algorithm will be used for the linedraw instruction. The values written to memory will be the color depth which is represented by a 4-bit value. Thus, 16 shades of color are allowed in the bitmap.
Translation is a simple operation whereby an integral offset is added to either the x or y values of the objects coordinates.
Skew is a form of translate which adds a variable amount to the x or y value based on position in the opposite value.
Error Handling
The maximum dimensions of the field addressable by this device is 256x256 (a 16-bit address) with x and y for each point being represented by an 8-bit value. However, with the operations this device provides the user, it would be quite simple to transform an object such that it lies outside the addressable 256x256 field.
The logical unit which operates on the objects will be built with overflow bits so that it can detect when the coordinates of an object exceed the addressable field. In such an event, the transformed value can not be written back to the register cell or to onboard memory because it would overflow the 8-bit register size. Instead, the original coordinates are left unchanged (no value is written back to the x1, y1, x2, and y2 registers) and an error flag is set within the object (object flags will occupy the upper nybble of the color register).
When the rasterize command is issued, the linedraw unit will ignore any object marked with an error. Thus, any line which would fall partially or completely outside the addressable field will not be drawn at all. This allows a simpler linedraw unit because all exceptional cases and overflows will be removed from the data before the linedraw stage.
Memory Addressing
The external memory will be addressed with a 16-bit value. However, only 8 output pins will be allocated to this purpose. First, the value of the high order byte is written out to an external register, which indexes the upper 8 bits of memory. One the second clock, the low order byte is output which, together with the output of the address register, indexes the full 16 bit address space.
Instructions
IN (REG ADDR) -- following input is written to register (REG ADDR)
OUT (REG ADDR) -- contents of (REG ADDR) is written out on output pins
LOADOBJ (IND) -- cell (IND) is loaded from RAM to the register cell.
STOOBJ (IND) -- values in register cell written out to RAM cell (IND)
TRANS -- replace register cell values with translated values
SKEW -- replace register cell values with skewed values
DRW -- draw current scene out to memory
Pins
Input Pins
8 pins for the input of instructions/data (data serially follows input
command)
Output Pins
8 pins for output of address (two transfers for an address) and data
(data output and memory address will never occur at the same time)
3 pins for shade data to memory
1 pin for register write enable
1 pin for memory write enable
1 pin for "Scene Complete" signal.
2 pins for device ready/controller ready handshake signals
7 pins to see the internal state of the controller
1 reset pin
= 32 pins, all unidirectional
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