Jeff Sandoval, Detecting Processor Instruction Cache for Platform Aware Compilation

Developing an optimizing compiler for high-performance computing is expensive; it requires a team of compiler experts and often takes three to five years of development and fine-tuning for a each target platform. Unfortunately, the rapid development cycles for modern computing systems can render a system obsolete before a mature compiler is even available. In response to this disparity, the Platform Aware Compilation Environment (PACE) project aims to build a compiler that can quickly and automatically adapt to future systems. The PACE compiler will employ powerful optimizations that tune a program to the precise hardware and software stack upon which it will run. For this purpose, the compiler must first collect accurate information about numerous characteristics of the underlying system, including the memory hierarchy, processor, parallel system, and native compiler. This talk will present our approach for measuring one such characteristic, the processor instruction cache. We will describe a microbenchmark that measures the instruction cache capacity and associativity and identifies which levels of cache are unified (i.e., caches that contain both data and instructions). Finally, we will present experimental results for several different architectures and discuss our approaches for automatically interpreting the results.