Sonali Dutta, Assertion Based Dynamic Verification of SystemC

Verification is essential, especially for hardware where the associated design and manufacturing cost is huge. SystemC has become a successful system level modeling language because it allows designers to model systems at several abstraction levels, from the most concrete (gate level) through the most abstract (system level) as well as it allows to co-design hardware and software in the same language. Increasing complexity of hardware-software co-design and decreasing time to market or chips have made SystemC verification crucial.

In this talk will show how we have contributed to this area by establishing an assertion based dynamic verification flow for SystemC. Our novel contribution includes:

1. Automatic runtime monitor generation.
2. Automatic instrumentation of systemC model under verification (MUV).
3. Establishing communication between generated runtime monitors, systemC simulation kernel and MUV.
4. Increasing efficiency of our flow: decreasing monitor generation time and monitor runtime overhead.