C0 = G0 + P0*CIN
C1 = G1 + P1*G0 + P1*P0*CIN
C2 = G2 + P2*G1 + P2*P1*G0 + P2*P1*P0*CIN
C3 = G3 + P3*G2 + P3*P2*G1 + P3*P2*P1*G0 + P3*P2*P1*P0*CIN
The carry generator in the CLA takes as its inputs the
propagate/generate signals and generates a carry for the next
bit. We then find the XOR of this carry bit with the next
propagate bit (AND of two input bits) to generate the sum.
The carry generator was broken up into bitwise carries to
not only economize on space, but to also illustrate the
tendency of the carry block to "blow up" as more bits are
added. It is because of this that carry-lookahead adders
are limited to 4-bits and are subsequently placed in
sequence (connected via the carry-out of the lower order bits)
for larger input combinations.
The following images are screen captures of the magic layouts
of each component followed by the logic expression that
describes each. NOTE: "+" = AND, "*" = OR.
C0 = G0 + P0*CIN
C1 = G1 + P1*G0 + P1*P0*CIN
C2 = G2 + P2*G1 + P2*P1*G0 + P2*P1*P0*CIN
C3 = G3 + P3*G2 + P3*P2*G1 + P3*P2*P1*G0 + P3*P2*P1*P0*CIN