The 8-bit latch is used for Karplas timing requirements. Inputs are expected to be valid only on rising/falling edges of the clock. If such inputs are connectly directly to logic, there will be spurious outputs from the logic because of the inherent instability of those inputs. Latches solve this problem by increasing the signal strength of the inputs so that logical "1" or "0" is stable throughout a clock rising or falling edge and stable assertion.