The Programmable Logic Array (PLA) is an array of AND and OR gates terminated by inverters that is generated by VLSI Design tools using pseudo NMOS logic. A PLA is general used as a control units, sometimes taking inputs from the outside and generating signals on different clock cycles according to its programming. Using a MEG file, which is simply a list of if/then and case statements derived from some Finite State Machine (FSM) representation, the PLA is generated. Our PLA cell was programmed using the following MEG file: