The adder unit performs addition and subtraction on 8-bit, 2's-compliment numbers. Under normal operation, the carry-in to the adder is held low and addition is performed. When the SUB_EN signal is held high, the second operand to the adder is inverted and carry-in is held high, thus performing standard 2's-compliment subtraction. The inversion of each bit is achieved by multiplexing the output of the inverters which compose the input latch and selecting the proper one for the requested operation. The slight difference in delay during subtraction caused by this is negligible.
Because the complexity of a full 8-bit carry-lookahead adder is rather high, and conversely, the speed gain is not that great, we opted to serially connect two 4-bit carry-lookahead adders instead (i.e. the carry-out of the lower order adder feeds the carry-in of the higher order adder). The carry-out of the most significant bit is used to indicate overflow. Technically this means we have an 8-bit group-ripple adder. We believe that a large amount of space was conserved by this decision.
To improve speed and also minimize space, we decided to forego the traditional carry-lookahead detection logic (which increases exponentially in size with each higher bit, even using pseudo-NMOS designs) in favor of a Manchester design provided by the textbook. The carry detection for each bit is calculated in parallel with the sum and passed on to the next higher bit. This design is relatively fast and can be made quite compact.
Despite this, the critical path for our circuit still passes through the adder, as our analysis shows.
