After testing our chips to a reasonable level, we can report that 3 of our chips were completely functional. One chip had Vdd and GND shorted together. This problem was most likely a wafer defect because it was the only chip that had this problem. Also, one chip was functional in a severely limited way. It passed a very specific simple set of test vectors; however, it would fail in almost every other set of test vectors. After removing the lid of the chip, we noticed that one of the wires from the tiny chip to its IC case was severed. The pin that was severed was a memory data pin which if wrong could cause the incorrectness of results that we observed. We can say that it was most likely this packaging problem that caused the chip's lack of functionality.
Our chip's speed performance is limited by its interface to an SRAM device. The maximum speed that we could run the chip at while maintaining the timing specifications of the SRAM device was 4.5 MHz. The closest clock frequency to 4.5 MHz that our testing hardware supported was 4.25 MHz, and our chips did function completely at this frequency. Thus, we can say that the characteristics of the MOSIS chip did not impede our performance.
We observed no damage in the shipping or the packaging of the chips other than the previously noted IC case wire problem.
We created a 4-bit CPU which uses load/store architecture. It has four 4-bit general purpose registers. Its instructions are 8-bit fixed length with a 4-bit opcode. The CPU addresses 512 bytes of off-chip memory that is split between instruction memory and data memory. The actual memory chip that we used was a Dallas Semiconductor DS1230Y.
We verified the functionality of the chip by running nine sets of test vectors which covered all instructions with many different operands. All sets of test vectors worked as expected on the three chips we referred to above as being completely functional. Many of our tests were rather specific in making sure that all logic values were properly propagated through the different paths for data flow. We used many values of A and 5 to try find data path bit errors. We had a great deal of observability at our pins. We could see register values, ALU outputs, state bits, fetched instructions, and the program counter as well as all memory addresses and data. Thus, we have a high degree of certainty in the correctness of the test vectors that we ran. The longest program that we ran using our CPU was about forty instructions long. We also tested other "long" programs which performed many varying tasks so that we could gain more confidence in the functionality of our physical chips.
WWW URL for project: http://www.owlnet.rice.edu/~wakin/vlsi
Project Members:
Anita Anderson (nitz@rice.edu)
Neal Jameson (nwjiii@rice.edu)
Mike Wakin (wakin@rice.edu)
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