Welcome to the VLSI Design I class at Rice University - Fall 1999

Elec 422 at Rice is designed to impart to the students the theory and application of VLSI design. The course includes a design project, where students design original circuits based on the material learned in class. The chips will be fabricated by MOSIS , and tested in the next class in this series, Elec 423 (VLSI II).

VLSI Design Faculty:
- Joe Cavallaro Office Hours: T 4-5, W 3-4, Th 4-5, Duncan Hall 3042.
Lab Assistants and Graders:
- Vishwas Sundaramurthy Office Hours: TBA, DH 3039
- Sridhar Rajagopal Office Hours: TBA, DH 3039

First Annual AMD/Rice University VLSI Design Contest Announcement
AMD Contest Presentations and Winners - Academic Year 1999-2000 Final
AMD Contest Presentations and Winners - Fall 1999

Fall 1999 Handouts - Administrative

Fall 1999 Handouts - Design Tools and Examples

Fall 1999 - Project Groups

A - Brian Becker, Douglas Haunsperger, Nicholas Humphries - Graphics Co-processor
B - Adam Blair, Eston Ferguson, Keith Layne, Joseph Shifflett - Multiplication/Division Co-processor
C - Timothy Danner, Reuven Lax, Anderson MacKay - GSAT Satisfiability Solver
D - Christopher Hopeman, Eric Johnson, Todd Wille - Multiplication/Division Co-processor
E - Ricardo Radaelli-Sanchez, Alexa Shoning, Hilary Scott - Mastermind Game
J - Jerry Huang, Jan-Michael Huber, Vassos Soteriou - Fraction to Binary Converter
X - Tsun-Yao Chang, Ben Gerdemann, Kwok-On Ng - Continuous Averager Co-processor
Y - Yonghui Cheng, Damian Dobric, Ping Tao, Shunxi Wang - FIR Filter Co-processor

MOSIS Run Status

The fall 1999 projects are to fabricated using the AMI 1.2 micron CMOS process through MOSIS. The class projects are to be included in the December 1999 MOSIS run.

Course Topics

The topics covered in this course include:

Overview of combinational Logic and minimization
Sequential logic and Finite State Machines
Overview of semiconductor physics
PMOS and NMOS transistors
CMOS fabrication technology (crystal growth, wafers, lithography, masks, doping, etc.)
Layout, design rules, stick diagrams
The latch-up effect, prevention, well contacts
Common structures (gates, compound gates, latches, shifters, PLA's)
Clocking strategies, 2-phase non-overlapping clock, Karplus methodology
Design Process - hierarchical design (regularity, modularity, locality)
Design verification tools (simulators, netlist comparators, DRC checkers, etc.)
MOS equations, second-order effects.
Biasing, AC and DC characteristics, load lines
Circuit parameters, parameter extraction
Timing, power, and size tradeoffs
Other CMOS structures: dynamic CMOS, pseudo NMOS, BiCMOS
Introduction to testing and testability
Analog CMOS

Sections of Course Manual - Not Complete

CAD Tool Man pages

Section 1 - cif2ps, cifplot, crystal, eqntott, esim, ext2sim, ext2spice, extcheck, fsleeper, irsim, magic, magicusage, meg, mkcp, mpla, net2ir, nutmeg, pplot, prepspice, rsleeper, sconvert, sim2spice, sleeper, spcpp, spice.
Section 3 - irsim-analyzer, mpack.
Section 5 - cmap, displays, dlys, dstyle, espresso, ext, glyphs, magic, mfbcap, mpanda, mpla, net, netchange, sim, simfile.

User contributed notes

Previous Years

About the VLSI Design class in Fall 1998 (last year), and Fall 1997, and Fall 1996, and Fall 1995

Joe Cavallaro

Last modified: 21 September 1999