Register File
=============

Inputs:   WRITE    (1)
	  ADDR     (4)
	  DATA_IN  (8)

Outputs:  DATA_OUT (8)

Functional description:
  ADDR is used to select one of the 16 8-bit words for reading or writing. If
  WRITE is asserted, the bits on DATA_IN will be loaded into this word. If
  WRITE is deasserted, then DATA_OUT will contain the bits of that word. (Note
  that DATA_OUT is undefined while WRITE is asserted.)

TODO: add some timing stuff here

Subcells: block of 16 latches (8)
	    - implemented with the usual 10T system
	  5->32 decoder
	    - implemented as a large NAND array
	  16->1 multiplexer (8)
	    - 1 T-gate for each input
	  
Leaf cells: static complementary latches              128 @ 10T each = 1280T
	    T-gates for the muxes		      128 @  2T each =  256T
	    5-input NAND gates for the decoder	       32 @ 10T each =  320T
	    inverters for the inputs to the decoder     5 @  2T each =   10T
	    inverters for the outputs of the decoder    5 @  2T each =   10T
								      ------
						               Total:  1876T 
Possible deficiencies of this design:
 - Fan-out of the decoder might be too high
    Solution: add some buffers
 - 16 T-gates are too many for one bus
    Solution: change the laws of physics to make it ok
 - Glitchy decoder could cause the mux to corrupt the latches
    Solution: temporary latches on the output of the decoder
 - 5-input NAND gates are not ok
    Solution: replace them with a shitload of logic