SAT Count
=========

Inputs:   LOAD     ( 1)
	  CLEAR    ( 1)
	  INCR     ( 1)
	  DATA_IN  (12)

Outputs:  DATA_OUT (12)

Functional description:
  The SAT counter holds a 12-bit unsigned integer. When LOAD is asserted, it
  assumes the value presented at DATA_IN. When CLEAR is asserted, the counter
  is reset to zero. On any clock cycle when INCR is asserted, the stored value
  is incremented. LOAD, CLEAR, and INCR are mutually exclusive.

TODO: add some timing stuff here

Subcells: Single bit counter
	  
Leaf cells: (shared components)
	    3-input NOR	(for the feedback T-gate)        1 @ 6T each = 6T
	    4 inverters (for controls and the above)	 4 @ 2T each = 8T
	    1 T-gate (the ground T-gate can be shared)	 1 @ 2T each = 2T
								      ---
								      16T

            (replicated components 12x)
	    4 inverters (3 for latch, 1 for carry out)   4 @ 2T each = 8T
	    3 T-gates (feedback, load, incr)		 3 @ 2T each = 6T
	    1 XOR (for incrementing)			 1 @ 8T each = 8T
	    1 NAND (for carry out)			 1 @ 2T each = 4T
								      ---
								      26T
								     *12
								     ----
								     312T
								     ====
							    Total:   328T

Possible deficiencies of this design:
 - may need a latch to prevent a race condition on INCR (race between
   carry_out and the sum). actually, I think we definitely need that