clear
stepsize 500
clock Vdd 1
vector A A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
vector B B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
vector out S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
ana A B C0 out S12

V A 101110111011 111111111111 111100001111 111100001111 111111111111 111111111111 111111111111 111111111111 000011110000 000011110000 101110001010 101110001010 000000001111 000000001111
V B 000000000000 111100001011 111100001011 000000000000 000000000000 000000000001 000000000001 111100011111 111100011111 111100001111 011111100001 011111100001 111100000000 111100000000

V C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1

R