This page presents the final simulation of our full chip with the I/O Pads. Our final simulation covers three iterations of the FIR filter process (calculating error and updating weights). This means a total of ~ 3 * 180 clock cycles! For this test we placed some inputs for X and D and calculated by hand the appropriate weight and error values. We set the Test0 and Test1 inputs of the chip to look at the state bits of the PLA so DB3 - DB0 are the state bits. The timing diagram below just shows the first iteration of the entire simulation. As you can see on the far right, the error is outputted and the ready signal goes high. Unfortunately IRSIM was having a problem displaying the timing diagram well since it is so large and we were unable to get clear Postscript files made for the remaining two iterations, but they can be seen by running the simulation in our sim directory.
Here are links to all of our command files (4 total: 1 main file and 5 included files):
nsekila.cmd fullchip_run.cmd fullchip_s1.cmd fullchip_s2.cmd fullchip_s3.cmd fullchip_s4.cmd
Simulation Results for Iteration 1:
