The PLA controls all of the elements of the circuit: MUXs, memory (latches and stacks), and 8-bit multiplier to provide the correct data flow through the system to 1) calculate the error and 2) update the weights of the filter. This control scheme is extremely complicated as each of these two phases takes approximately 86 cycles and the multiplier and adder/accumulator are re-used extensively for different computations which requires careful control of the MUXs. In addition, the multiplier is constantly producing an output so it is essential that the load signal to load the inputs to the multiplier is done on the correct clock cycle to obtain the correct output. Since our system requires repetitive multiplication and accumulation for each filter tap weight, we created two Ring Counters that count to 8 in order to keep track of when a multiply operation completes and when we have completed 8 multiply operations (8 operations are required because we have 8 filter taps). The counter that keeps track of how many clock cycles have transpired since the multiplication started simply runs off CLKA and CLKB so it is constantly counting. The counter that keeps track of how many multiplications have been performed is controlled by two signals from the PLA, one which is like a CLKA signal and one which is like a CLKB signal. These two signals are sent out from the PLA on two different clock cycles to insure proper operation.
The following sections describe the details of the PLA: