User Commands MEG(1) NAME meg - Mealy finite state machine compiler SYNOPSIS meg [options] input_file DESCRIPTION Meg (Mealy Equation Generator) is a finite state machine compiler. It translates a high level language desription of a finite state machine into several implementation and simu- lation formats. Meg uses the Mealy model for finite state machines, in which outputs are dependent upon inputs as well as state. Input is read from the named file or from stdin if '-' is specified. Meg can be used to produce boolean equations in the eqn- tott(1) format, truth tables in the PLA(5) format, or truth tables in the espresso(5) format. Meg also generates output for the functional simulators Slang and N.2.mpc, and input for the Sungrab directed graph program. OPTIONS -s Print summary information in the file meg.summary. -t Generate a human readable truth table in the file meg.summary. -T Generate a truth table in PLA(5) format in the file meg.tt. -s Generate a Slang description of the finite state machine to stdout. See the Slang Slinger's Cyclopedia for a description of Slang. -i Generate a truth table in ESPRESSO(5) format in the file meg.imp. This format can be used as input to espresso(1) and kiss(1). -e Generate equations compatible with eqntott(1) to std- out. -n or -N Generate an N.2 description to stdout. N.2 is a func- tional simulator that is commercially available from ENDOT, Inc. See the OUTPUT FORMATS section below for more details. -g or -G Generate a GRAB description to stdout. GRAB is a SunOS 5.6Last change: Advanced Copy -- DO NOT DISTRIBUTE 1 User Commands MEG(1) directed graph language that can be used to print or display the finite state machine on a raster device. GRAB is still in development at this time. See the OUTPUT FORMATS section below for more details. When multiple options are selected that write output to std- out they appear in the following order: N.2, GRAB, Slang, and Equations. INPUT FORMAT A Meg program is composed of the following sections: INPUTS : signal1 signal2 ... ; An input signal list consists of the keyword INPUTS followed by a colon and a white-space separated list of input signal names, terminated by a semicolon. If the FSM has no inputs this line must be omitted. OUTPUTS : signal1 signal2 ... ; An output signal list consists of the keyword OUTPUTS fol- lowed by a colon and a white-space separated list of output signal names, terminated by a semicolon. If the FSM has no outputs this line must be omitted. RESET ON input_signal TO [STATE] reset_state; This optional statement specifies the reset signal and state. When the signal input_signal is asserted, the FSM is forced to reset_state while outputting any signals specified in the reset_state specifier. The reset_state specifier is in the next_state syntax, described below. The signal input_signal must appear in the INPUTS list. These sections are followed by a list of states with the following format: state_name : control ; Each state is must be given a unique state name. It's con- trol must be specifed in one and only one of the following manners: IF [NOT] input THEN next_state ELSE next_state ; GOTO next_state ; CASE ( input_selector_list ) cases ENDCASE [default] ; Next_states are specified by a state name optionally fol- lowed by a list of output signals to be asserted, enclosed in parentheses. next_state ::= state_name [ ( output_signal_name ... ) ] ; SunOS 5.6Last change: Advanced Copy -- DO NOT DISTRIBUTE 2 User Commands MEG(1) Output signals may be set to a specific value using the syn- tax: output_signal_name ::= signal_name [ = { 0 | 1 | ? } ] Signals that do not have the "equals value" syntax are asserted to 1. Signals that do not appear in the list are asserted to 0. Cases is a list of case selectors of the form: { 0 | 1 | ? }+ => next_state ; Where the number of bit entries is the same as the number of input signals in the input_selector_list. When the input-selector-list matches the bit pattern of the selector, control is transfered to next-state. An error occurs if the same pattern is multiply specified. Input patterns that do not match a case selector result in the default case being taken, or an error if the default is not specified. The form of default is: => next-state ; All next-state transitions must be explicitly specified. The special state name LOOP may be used to specify that the next state is the same as the current state. The special state name ANY may be used to specify that the state transi- tion and its outputs are all don't cares. This is usually only used for input conditions that can't occur. This information is used by the logic optimizers to reduce the size of the PLAs. Comments may appear anywhere in a Meg program. They begin with a double dash "--" and terminate with the end of the current line. The C pre-processor can be invoked before the input is parsed. This enables the limited use of symbolic names in the specification of the FSM. This is illustrated in the example below. OUTPUT FORMATS N.2 Output Format The N.2 output option produces a N.2 module containing a when process to implement the pla. The module has a port for each input and each output. There is also an output port for the binary encoding of the finite state machine SunOS 5.6Last change: Advanced Copy -- DO NOT DISTRIBUTE 3 User Commands MEG(1) source (assigned from 0 in the order of declaration in the Meg source), and two input ports for clocks, SampleClock and AssertionClock. The logic samples its inputs on the falling edge of Sample- Clock and asserts its outputs on the rising edge of Asser- tionClock. This is characteristic of static PLA behavior. The initial state is the first state in the Meg input file. GRAB Output Format The name of the graph is the root of the input file name. Oval nodes are states, named with the Meg state name. Rect- angular nodes are arcs, named fromstate_n, where fromstate is the name of the state that the arc eminates from, and n is the order of that arc in the state starting at 0. EXAMPLE The following example illustrate the use of Meg: -- OPUS Multibus controller, Version 2.0, 2/15/85 INPUTS: INIT OP1 OP2 SWR MACK; OUTPUTS: WAIT MINIT MRD SACK MWR DLI; -- Define the encoding for the processor operations -- The C preprocessor does textual substitution on these macros. #define OP OP1 OP2 #define NOP 0 0 #define HALT 0 1 #define READ 1 0 #define WRITE 1 1 #define XOP ? ? -- describe the reset logic reset on INIT to swr0(MINIT WAIT=?); -- wait for slave write from multibus to activate us -- Note the specification of a don't care output. swr0: if SWR then swr1(MINIT WAIT=? DLI SACK) else swr0(MINIT WAIT=?); -- wait for slave write to go away swr1: if SWR then swr1(MINIT WAIT=? SACK) else op0; -- wait for request from processor -- The C preprocessor expands the symbolic name OP into two input -- signal names, and the symbolic OPs, e.g. NOP, into their binary encoding . -- Note the use of the special state ANY to indicate a don't care -- state transition. op0: case (SWR MACK OP) 0 ? NOP => op0; SunOS 5.6Last change: Advanced Copy -- DO NOT DISTRIBUTE 4 User Commands MEG(1) 0 ? HALT => swr0(MINIT WAIT=?); 0 0 READ => op1(WAIT MRD); 0 0 WRITE => op1(WAIT MWR); 0 1 READ => op0(WAIT); 0 1 WRITE => op0(WAIT); 1 ? XOP => swr1(MINIT WAIT=? DLI SACK); endcase => ANY; -- after starting transaction, wait for acknowledge op1: case (SWR MACK OP) 0 0 READ => op1(MRD); 0 0 WRITE => op1(MWR); 0 1 READ => op0(DLI); 0 1 WRITE => op0; 1 ? READ => swr1(MINIT WAIT=? DLI SACK); 1 ? WRITE => swr1(MINIT WAIT=? DLI SACK); endcase => ANY; SEE ALSO espresso(1), kiss(1), mpla(1), eqntott(1), peg(1), espresso(5), pla(5). R. Rudell, A. Sangiovanni-Vincentelli, G. De Micheli, A Finite-State Machine Synthesis System. AUTHOR David A. Wood BUGS Meg is a direct descendent of Peg, by Gordon Hamachi, and inherits many bugs and limitations. SunOS 5.6Last change: Advanced Copy -- DO NOT DISTRIBUTE 5