1. ELEC 522: Advanced
University: Fall 2022, Ryon Lab RYN B10
Credits: 3 credit hours
Tuesday and Thursday, 1:00 to 2:20pm RYN B10
Lab/teaching Assistant: Thomas Keller,
DCH 3041, firstname.lastname@example.org
4. Office Hours: After class or by appointment
Policies: Grading will be based on the projects
and presentations assigned during the semester.
Absence Policies: Attendance and
participation in class is expected. In general, the class on Tuesday is lecture
oriented, while the class on Thursday is often focused on design tools and
7. Course Materials:
recommended books and e-books provide background readings on FGPA design and
- Louise Crockett,
Ross Elliot, Martin Enderwitz, Bob Stewart, The Zynq Book, Embedded
Processing with the ARM Cortex-A9 on the Xilinx Zynq-7000 All Programmable
SoC, Strathclyde Academic Media, 2014, ISBN-13: 978-0-9929787-0-9, E-Book
available for download from: http://www.zynqbook.com/
- Ryan Kastner,
Janarbek Matai, and Stephen Neuendorffer, Parallel Programming for FPGAs,
2018, E-Book available for download from: http://kastner.ucsd.edu/hlsbook/
- Louise H.
Crockett, David Northcote, Craig Ramsay, Fraser D. Robinson, Robert W.
Stewart, Exploring Zynq MPSoC With PYNQ and Machine Learning Applications,
Strathclyde Academic Media, 2019, ISBN-978-0-9929787-5-4, E-Book available
for download from: https://www.zynq-mpsoc-book.com/
- Wayne Wolf,
FPGA-Based System Design, Prentice Hall, 2004, ISBN 0-13-142461-0
on Chapters 1, 3, 6, 7. http://www.amazon.com/FPGA-Based-System-Design-Prentice-Semiconductor/dp/0131424610/ref=sr_1_3/102-0171952-4496933?ie=UTF8&s=books&qid=1188319895&sr=1-3
Tuttlebee, Editor, Software Defined Radio, Baseband Technology for 3G Handsets
and Basestations, John Wiley and Sons, 2004, ISBN 0-470-86770-1
on Chapters 1, 2, 3, 4, 5, 6, 7, 10, 11. http://www.amazon.com/Software-Defined-Radio-Technologies-Basestations/dp/0470867701/ref=sr_1_2/102-0171952-4496933?ie=UTF8&s=books&qid=1188320142&sr=1-2
materials: Current papers and design tool tutorials posted to Canvas.
Papers (from IEEE
Explore) are on FPGA and ASIP design, and example architectures, including:
- From ASIC to
ASIP: The Next Design Discontinuity
Architecture: Principles and Progression
Acceleration for Big Data Analytics: Challenges and Opportunities
- The Evolution of
Domain-Specific Computing for Deep Learning
General-Purpose Code Into Dynamically Scheduled Circuits
Processors for Wireless Systems
- Energy and
Time-Efficient Matrix Multiplication on FPGAs
Synthesis for FPGAs: From Prototyping to Deployment
- FPGA based
Embedded Processing Architecture for the QRD-RLS Algorithm
QR Decomposition for MIMO Detection in OFDM Systems
Technology Roadmap for Semiconductors 2.0
Specific Course Information:
Catalog Description: Design and analysis
of algorithm-specific VLSI processor architectures. Topics include the
implementation of pipelined and systolic processor arrays. Techniques for
mapping numerical algorithms onto custom processor arrays. Course includes
design project using high-level VLSI synthesis tools.
Prerequisites: A course in Digital
Systems Design such as ELEC 326/327 is recommended. An introductory course in
VLSI System Design is useful. Background in computer architecture, computer
arithmetic, and signal processing is also helpful. C++ language programming is
useful as well as compiler/debugging tools such as Eclipse and Visual Studio.
Elective Status: ELEC 522 is a
graduate elective. Undergraduates may take the course as a Specialization
course in Computer Engineering in consultation with their advisor.
d. Projects for Fall
2022 and Presentation: Approximately
6 individual project assignments on ASIC and FPGA Design using the Xilinx
System Generator tools, along with Xilinx Vivado tools. Some assignments will
use Xilinx Vitis for the Zynq chip for embedded systems. As time permits, we
may use Synopsys DC Ultra for ASIC synthesis and the Cadence SOC Encounter
tools in the ASIC flow. For System on Chip integration the Xilinx Vitis HLS and
Vivado for high level synthesis will be used. A student presentation will be
given in class on progress on several of the projects. Previous year topics
have included a systolic array co-processor for matrix factorization and
solution of systems of linear equations. A tentative list of projects includes
accelerator designs for linear systems:
/ CUDA Intro
on FPGA / GPU
2022, we may include project components using GPU programming and acceleration
as GPU prototypes are often used in developing FPGA or ASIC accelerators.
9 Specific Goals for
a. Outcomes: The goals of the course are to study design methodologies
for application-specific processors for applications particularly in wireless
communications and machine learning. The course includes a design project
initially targeted to an FPGA. The student will be able to specify, design,
simulate, assess, and verify custom accelerators and integrate experimentally
into a System on Chip (Soc) platform.
b. Course Outcomes:
Related to ABET Criterion 3 numbers 1 through 7:
The relationships to seven criteria are
listed with 1, 2, and 3. (with 3 as most related.)
An ability to identify, formulate, and
solve complex engineering problems by applying principles of engineering,
science, and mathematics.
An ability to apply engineering design to
produce solutions that meet specified needs with consideration of public
health, safety, and welfare, as well as global, cultural, social, environmental,
and economic factors.
An ability to communicate effectively with
a range of audiences.
An ability to recognize ethical and
professional responsibilities in engineering situations and make informed
judgments, which must consider the impact of engineering solutions in global,
economic, environmental, and societal contexts.
An ability to function effectively on a
team whose members together provide leadership, create a collaborative and
inclusive environment, establish goals, plan tasks, and meet objectives.
An ability to develop and conduct
appropriate experimentation, analyze and interpret data, and use engineering
judgment to draw conclusions.
An ability to acquire and apply new
knowledge as needed, using appropriate learning strategies.
10: Topics and Course
Contents: The topics covered
in this course include:
methodology for ASIC and FPGA implementations
- GPU organization
and programming using C++ , CUDA and Visual Studio
- FPGA hardware
structures and fabrics
- Review of Combinational
Logic, Sequential Machines, and Architecture
- High-level VLSI
synthesis and design tools including Synopsys, Cadence, Mentor Graphics,
with CAD algorithm overview for floorplanning, placement, and routing in
- High-level DSP
algorithm simulation and code (VHDL/Verilog) generation using Xilinx System
Generator, and Xilinx Vivado HLS.
- Design and
analysis of algorithm-specific VLSI processor architectures. Topics
include the implementation of pipelined and systolic processor structure.
Techniques for mapping numerical algorithms onto custom processor arrays, including
Application Specific Instruction Processors (ASIPs).
Design frameworks for systems containing custom and general-purpose units.
using Xilinx System Generator, Xilinx Vitis HLS, Xilinx Vivado, Xilinx
Vitis, and Xilinx FPGAs with emphasis on the Xilinx Zynq chip containing
ARM core and FPGA fabric.
We will use the VLSI Digital
Design Lab, RYN B10 in Ryon Engineering Laboratory, with the Xilinx ZedBoard and
Pynq-Z1 University Development Boards which contains the Xilinx Zynq-7000 chip for
the course; the Rice CLEAR Linux cluster for access to a Xilinx Alveo FPGA
board, Synopsys/Cadence VLSI design tools via Xwindows using MobaXterm in
addition to the laboratory PCs in RYN B10; Canvas at Rice for notes and project
submission. NVIDIA GTX 1660 GPU with CUDA 11.7 and Visual Studio 2022 Community
Rice Honor Code: The Honor Code will
apply to individual projects. Each project/presentation will state the specific
Students with Disabilities: Any
student with a disability requiring accommodations in this course is encouraged
to contact the instructor after class or during office hours. Additionally,
students will need to contact Disability Support Services in the Ley Student
Updates: Consult the class Canvas page for
updates to information contained in the syllabus.
20 August 2022