1. ELEC 522: Advanced VLSI Design

Rice University: Fall 2021, Ryon Lab RYN B10

 

2. Credits: 3 credit hours

Lectures: Tuesday and Thursday, 1:00 to 2:20pm RYN B10

 

3. Course Instructor: Joe Cavallaro , DCH 3042, cavallar@rice.edu

Lab/teaching Assistant: Yonggan Fu, yf22@rice.edu

 

4. Office Hours: After class or by appointment

 

5. Grade Policies: Grading will be based on the projects and presentations assigned during the semester. A final exam on the text and readings may be given.

 

6. Absence Policies: Attendance and participation in class is expected. In general, the class on Tuesday is lecture oriented, while the class on Thursday is often focused on design tools and laboratory tutorials.

 

7. Course Materials:

These recommended books and e-books provide background readings on FGPA design and applications.

Emphasis on Chapters 1, 3, 6, 7. http://www.amazon.com/FPGA-Based-System-Design-Prentice-Semiconductor/dp/0131424610/ref=sr_1_3/102-0171952-4496933?ie=UTF8&s=books&qid=1188319895&sr=1-3

Emphasis on Chapters 1, 2, 3, 4, 5, 6, 7, 10, 11. http://www.amazon.com/Software-Defined-Radio-Technologies-Basestations/dp/0470867701/ref=sr_1_2/102-0171952-4496933?ie=UTF8&s=books&qid=1188320142&sr=1-2

 

Other supplemental materials: Current papers and design tool tutorials posted to Canvas.

Papers (from IEEE Explore) are on FPGA and ASIP design, and example architectures, including:

 

8. Specific Course Information:

 

a. Catalog Description: Design and analysis of algorithm-specific VLSI processor architectures. Topics include the implementation of pipelined and systolic processor arrays. Techniques for mapping numerical algorithms onto custom processor arrays. Course includes design project using high-level VLSI synthesis tools.

 

b. Prerequisites: A course in Digital Systems Design such as ELEC 326/327 is recommended. An introductory course in VLSI System Design is useful. Background in computer architecture, computer arithmetic, and signal processing is also helpful.

 

c. Elective Status: ELEC 522 is a graduate elective. Undergraduates may take the course as a Specialization course in Computer Engineering in consultation with their advisor.

 

d. Projects for Fall 2021 and Presentation: Approximately 6 project assignments on ASIC and FPGA Design using the Xilinx System Generator tools, along with Xilinx Vivado tools. Some assignments will use Xilinx Vitis for the Zynq chip for embedded systems, and Synopsys DC Ultra for ASIC synthesis. We will also use the Cadence SOC Encounter tools in the ASIC flow for System on Chip integration and Xilinx Vivado HLS for high level synthesis. A student presentation will be given in class on several of the projects, and additional presentations of research papers will be assigned for discussion. Previous year topics have included a systolic array co-processor for matrix factorization and solution of systems of linear equations. A final exam on the text and readings may be given. A tentative list of projects includes accelerator designs for linear systems:

 

ELEC_522_Proj_1_Sysgen_Intro

ELEC_522_Proj_4_Vivado_HLS_CORDIC

ELEC_522_Proj_2_Matrix_Mult

ELEC_522_Proj_5_QR_Array

ELEC_522_Proj_3_Vivado_HLS_Matrix_Mult

ELEC_522_Proj_6_4x4_Linear_System_Solver

 

For 2021, we may include alternative projects using Python with the Pynq (Python on Zynq) environment on the new Pynq-Z1 boards for Machine Learning accelerators and applications.

 

9 Specific Goals for the Course:

 

a. Outcomes: The goals of the course are to study design methodologies for application-specific processors for applications particularly in wireless communications. The course includes a design project initially targeted to an FPGA. The student will be able to specify, design, simulate, assess, and verify custom accelerators and integrate experimentally into a System on Chip (Soc) platform.

 

b. Course Outcomes: Related to ABET Criterion 3 numbers 1 through 7:

The relationships to seven criteria are listed with 1, 2, and 3. (with 3 as most related.)

 

1

An ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics.

3

2

An ability to apply engineering design to produce solutions that meet specified needs with consideration of public health, safety, and welfare, as well as global, cultural, social, environmental, and economic factors.

3

3

An ability to communicate effectively with a range of audiences.

1

4

An ability to recognize ethical and professional responsibilities in engineering situations and make informed judgments, which must consider the impact of engineering solutions in global, economic, environmental, and societal contexts.

1

5

An ability to function effectively on a team whose members together provide leadership, create a collaborative and inclusive environment, establish goals, plan tasks, and meet objectives.

2

6

An ability to develop and conduct appropriate experimentation, analyze and interpret data, and use engineering judgment to draw conclusions.

3

7

An ability to acquire and apply new knowledge as needed, using appropriate learning strategies.

1

 

10: Topics and Course Contents: The topics covered in this course include:

 

Laboratory Use:

We will use: the VLSI Digital Design Lab, RYN B10 in Ryon Engineering Laboratory with the Xilinx ZedBoard and Pynq-Z1 University Development Boards which contains the Xilinx Zynq-7000 chip for the course; the Rice CLEAR Linux cluster for access to Synopsys/Cadence VLSI design tools via Xwindows using MobaXterm in addition to the laboratory PCs in RYN B10; Canvas at Rice for notes and project submission.

 

11. Rice Honor Code: The Honor Code will apply to both individual and small group projects. Each project/paper/presentation/exam will state the specific details.

 

12. Students with Disabilities: Any student with a disability requiring accommodations in this course is encouraged to contact the instructor after class or during office hours. Additionally, students will need to contact Disability Support Services in the Ley Student Center.

 

13. Updates: Consult the class Canvas page for updates to information contained in the syllabus.


Joe Cavallaro Updated 14 August 2021