FAQs:
Cadence has released a new waveform-viewing and -analysis tool named ``Signalscan Waves'', which replaces SimWaves. To start the new tool, simply type
signalscan &
at the shell prompt.
To access the signalscan documentation, do the
following:
Use the menu entry ``File->New->Library...'' from the CIW. If you are running version 4.4.2.100.22 or later of Cadence, you can also use the ``File->New->Library...'' menu entry from the Library Manager. (If you see ``Loading NCSU Library Manager customizations...done'' in the ``Messages'' field of the Library Manager immediately after starting Cadence, you can use ``File->New->Library...'' from the Library Manager. The CDK customizations cannot be hooked into earlier versions of the Library Manager.)
If you want to make a design library for an SCMOS technology, you probably should just attach your library to one of the design libraries that comes with the CDK. This is as simple as choosing the appropriate entry in the popup menu that appears when you select the ``Attach to existing tech file'' option.
Alternatively, if you want to make your own technology library (for example, so you can customize parasitic capacitances, or you might have a non-SCMOS technology file) choose the ``Compile tech file'' option. To compile a technology library for a non-MOSIS process, choose ``other...'' in the popup menu, and type the name of the tech file you wish to use in the form that appears.
Note that you can also hook your own SKILL routines into the library creation process.
(The technology libraries distributed with the CDK have names like NCSU_TechLib_xxxYY, where xxx is the vendor name and YY is the minimum (drawn) device length. Examples are NCSU_TechLib_tsmc03 and NCSU_TechLib_ami06 for the TSMC 0.30um (drawn) and the AMI 0.6um (drawn) processes respectively. If you choose the ``attach'' option, the appropriate technology library is automatically added to your Library Manager.)
How can I tell which technology library my design library is attached to?
In the library manager, hold down the right mouse button over your design library name. Select ``Properties...'' from the menu that pops up. If your design library is attached to a technology library, there'll be a field named techLibName on the form that appears; it contains the name of the technology library your design library is attached to.
How can I attach a technology library to a design library that already exists?
In the library manager, hold down the right mouse button over your design library name. Select ``Attach tech library...'' from the menu that pops up. In the form that appears, make sure the name of your design library appears next to ``Design library:''. Select the technology you want to use from the ``Technology library:'' pulldown menu. Click ``OK'' and you're done!
When you edit a design, Cadence establishes an ``edit lock'' so someone else won't be able to edit the file until you're done. Sometimes (for example, when your session crashes and you can't get back on the same computer), the edit lock becomes stranded, meaning that it hangs around (even though you're not editing the file any more) and prevents you and others from doing any edits.
You can try manually releasing the edit lock by using a program
called clsAdminTool. Try the following:
> prompt.
If the above doesn't work, you may have to just copy the cell in question to a new name and edit that instead.
In a nutshell, you need to have the owner of the library set the AFS
``k'' (file locking) permission bit for ``system:authuser'' (or
whichever user ID or PTS group you're accessing the library under) on
the library and all its subdirectories. This is easy to do with the
find command, e.g. (assuming the library already had ``r''
and ``l'' AFS permissions set for system:authuser):
find <library_directory> -type d -exec fs sa {}
system:authuser rlk \;
(Just FYI, here's what we've been able to determine: the Library Manager needs to lock one or more files in the library, but doesn't understand how to handle the response from AFS if the k bit isn't set for the UID requesting the lock. The result is a segmentation fault that takes down the entire toolset. Things seem to work fine under UFS and NFS, according to what we've heard. If anybody has any further light to shed on this subject, please drop a note to cadence_help@ncsu.edu.)
How can I tell what layer this polygon's on? Or what library this instance is from?
Click on it and see the info echoed in the CIW, or click on it and hit q to bring up the Properties form.
How do I simulate my extracted layout/schematic?
Circuit simulation uses Analog Artist. From your extracted circuit/schematic, choose the ``Tools->Analog Artist...'' menu entry. The CDK includes transistor models for both HSPICE and Spectre. Logic simulation is done with Verilog-XL.
As an aid in circuit simulation of digital circuits, the CDK includes BitGen, an easy-to-use program that converts bit streams of 1's and 0's to analog voltage sources (pwl and pulse) that SPICE-like programs understand. BitGen is accessible through Artist's ``Setup->Stimulus->Run BitGen...'' menu entry.
I want to make my own menus in layout and schematic windows. How can I do that?
Easily. The CDK allows users to install their own menus defined by a simple configuration file. You can also hook in SKILL routines to be called at various stages in the library compilation process. Check out the documentation for instructions.
Setting the environment variable SKIP_CDSLIB_MANAGER keeps the Library Manager from automatically being started. Setting the environment variable SKIP_CDS_DIALOG keeps the ``xmesg'' dialog from appearing.
The NCSU CDK is © NC State University, 1998-2000. Users are free to use or modify the NCSU CDK as appropriate as long as this notice appears in it. You are also advised that you use the NCSU CDK at your own risk. By using the NCSU CDK, you assume all liability for any resulting errors and problems.