The following layers are common to all MOSIS CMOS processes:
CDK layer name | Description | Stream layer number | CIF layer abbreviation |
---|---|---|---|
nwell | N-well | 42 | CWN |
pwell | P-well | 41 | CWP |
active | active (diffusion) | 43 | CAA |
nactive* | N-active | 43 | CAA |
pactive* | P-active | 43 | CAA |
nselect | N-select (ion implant) | 45 | CSN |
pselect | P-select (ion implant) | 44 | CSP |
poly | polysilicon | 46 | CPG |
metal1 | first-layer metal | 49 | CMF |
ca | metal1-active contact (obsolete; use cc instead) | 48 | CCA |
cp | metal1-polysilicon contact (obsolete; use cc instead) | 47 | CCP |
cc | generic contact (metal1 to active or polysilicon) | 25 | CCC |
via | metal1-metal2 contact | 50 | CVA |
metal2 | second-layer metal | 51 | CMS |
pad | wirebond pad marker | 26 | XP |
glass | overglass cut | 52 | COG |
cap_id | capacitor marker | NA | NA |
res_id | resistor marker | NA | NA |
dio_id | diode marker | NA | NA |
*nactive and pactive are simply convenience layers for the user, not mask layers, and are treated as ``active'' for purposes of streaming out, DRC, and extraction.
The following table shows which active processes support which optional technology features. See below for the mask layers that correspond to the technology features.
Technology Feature | AMI 1.6um | AMI 0.6um | HP 0.6um | HP 0.4um | TSMC 0.4um (4M) | TSMC 0.4um (4M2P) | TSMC 0.3um | TSMC 0.2um |
---|---|---|---|---|---|---|---|---|
electrode | + | + | + | |||||
poly capacitor | ||||||||
high-res implant | + | |||||||
npn | + | |||||||
third-layer metal | + | + | + | + | + | + | + | |
fourth-layer metal | + | + | + | + | + | |||
fifth-layer metal | + | + | ||||||
sixth-layer metal | + | |||||||
metal-metal cap | + | + | ||||||
silicide block | + | + | + | + | ||||
thin-oxide cap | + | |||||||
high-voltage FETs | + | + | + | + |
Layers that correspond to optional technology features:
Technology Feature | CDK layer names | Description | Stream layer number | CIF layer abbreviation |
---|---|---|---|---|
electrode | elec | second polysilicon | 56 | CEL |
ce | metal1-electrode contact (obsolete; use cc instead) | 55 | CCE | |
poly capacitor | polycap | lower poly for thin-oxide capacitor | 28 | CPC |
high-res implant | highres | implant for high-resistance elec (poly2) | 34 | CHR |
npn | pbase | base for vertical NPN transistors | 58 | CBA |
cactive* | marker for collector of NPN transistors | 43 | CAA | |
third-layer metal | metal3 | third metal | 62 | CMT |
via2 | metal2-metal3 contact | 61 | CVS | |
fourth-layer metal | metal4 | fourth metal | 31 | CMQ |
via3 | metal3-metal4 contact | 30 | CVT | |
fifth-layer metal | metal5 | fifth metal | 33 | CMP |
via4 | metal4-metal5 contact | 32 | CVQ | |
sixth-layer metal | metal6 | sixth metal | 37 | CM6 |
via5 | metal5-metal6 contact | 36 | CV5 | |
metal-metal cap | metalcap | inter-metal layer for capacitor | 35 | CTM |
silicide block | sblock | silicide implant block for resistor | 29 | CSB |
thin-oxide cap | cwell | well implant for linear thin-oxide capacitor | 59 | CWC |
high-voltage FETs | tactive | thick oxide | 60 | CTA |
*cactive is simply a convenience layer for the user, not a mask layer, and is treated as ``active'' for purposes of streaming out, DRC, and extraction.
Please see MOSIS' list of layers for the official word.