JAWs Algorithm Schedule

06 November 1998

Instructions: 8-bit fixed length instructions

Registers: 4 4-bit general purpose registers, a 4-bit memory access register, an 8-bit program counter (PC)

Store instructions in Instruction Memory (IM)
Initialize PC and all regs at power up

Fetch instruction at PC
Decode instruction - break instruction into

1. Inst[7-4] - opcode
2. Inst[3-2] - regds
3. Inst[1-0] - regs
4. Inst[3-0] - immediate

Asserted Signals by Stage and Instruction

Instruction Fetch Stage
IF and MemRead are asserted in order to obtain the instruction from memory.

RegRead/ALUExec Stage

BEZ/BGZ - Assert RegRead and Branch. Note that the BranchZ control for the mux which chooses betwen the equal or greater than logic is hardwired from the opcode. If the branch is taken: the concatenated rs amd rm will be fed into the PC.
SLL - Assert RegRead and ALUSrc2. Not that rds is padded with 00.
ADD - Assert RegRead.
SUB - Assert RegRead.
NOT - Assert RegRead.
AND - Assert RegRead.
OR - Assert RegRead.
LW - Assert MemRead. Note: concatenated rs and rm is used for the memory address.
SW - Assert RegRead and MemWrite Note: concatenated rs and rm is used for the memory address.
SETM - Assert RegRead, SetRM and MRegSrc.
SETMI - Assert SetRM.
ADDI - Assert RegRead, ImpReg3, FourImm, ALUSrc2.
LDI - No control signals asserted.
ZERO - No control signals asserted.

Write Back Stage

BEZ/BGZ - No control signals asserted.
SLL - Assert RegWrite.
ADD - Assert RegWrite.
SUB - Assert RegWrite.
NOT - Assert RegWrite.
AND - Assert RegWrite.
OR - Assert RegWrite.
LW - Assert RegWrite.
SW - No control signals asserted.
SETM - No control signals asserted.
SETMI - No control signals asserted.
ADDI - Assert RegWrite.
LDI - Assert RegWrite, ImpReg3 and ImmData.
ZERO - Assert RegWrite and WriteZero.

06 November 1998
Control signals now specified by instruction and state. Includes new instruc SETM from register.

Changes made to reflect timing analysis.

22 September 1998

Original submitted.