THE BOMB!

FUNCTIONAL DESCRIPTION

The BOMB! is a miniature CPU that has a limited instruction set, yet still performs all the essential CPU operations. The main operations can be separated into arithmetic, data transfer, control, and miscellaneous categories. The arithmetic operations are very basic, but enough to be used in a simple application. The data transfer instructions provide all the necessary load and store commands between memory and the registers in the CPU. There is only one control instruction: branch. The lack of other instructions such as branch on comparisons is due to space and complexity issues. We believe basic functionality can be achieved with just one branch instruction. Finally, the miscellaneous instructions include one common instruction, NOP, which speaks for itself, and another instruction, IDLE, which is can be used for applications common to microcontrollers.

ISSUES

The challenges faced in creating the CPU come on several levels. On the highest level, we were challenged with deciding upon the best combination of instructions our CPU would execute. There are obviously a slew of possible instructions that we could have chosen, but our goal was to choose a set which would keep our CPU simple, while also maintaining the basic traits of a full fledged CPU. We also wanted to provide an instruction which would make the chip more application oriented, and hence we included the IDLE instruction.

On a lower level, the challenge was efficiently communicating between one piece of the CPU with another. To ensure an efficient and successful design, we had to make sure the timing of the signals from the PLA matched those of the ALU, PC, and registers. Also, we had to decide upon a bus design which both saved space, while still providing flexibility in terms of which components could read or write from the bus.

On the lowest level, the substrate connections proved to be a very time consuming problem. Since the substrate errors did not appear until the entire chip was connected, fixing the problems often required very time consuming rewiring and re-layout of the components.

INSTRUCTION SET SPECIFICATION

All instructions are 4 bits in length. The operands are all implicit.

For the ARITHMETIC/LOGICAL instructions, the implicit operands are either the register and the accumulator, or just the accumulator.

For the DATA TRANSFER and CONTROL instructions, the implicit memory operand is the 8-bit value specified by the two memory locations immediately following the instruction. The first four bits immediately following the instruction specify bits 7-4 of the memory address, and the next four bits specify bits 3-0 of the memory address. So, the DATA TRANSFER and CONTROL instructions can be thought of as 12-bit instructions, where the first 4-bits specify the instruction, and the following 8-bits specify the memory location.

The MISC/HARDWARE instructions have no operands.

OPCODE	INSTRUCTION			DESCRIPTION
ARITHMETIC/LOGICAL
0000	ADD			ADDs the value in the register to the value on the accumulator and places the result in the accumulator
0001	SUB			SUBTRACTs the value in the register to the value on the accumulator and places the result in the accumulator
0010	AND			Performs a logical AND on the value in the register to the value on the accumulator and places the result in the accumulator
0011	OR			Performs a logical OR on the value in the register to the value on the accumulator and places the result in the accumulator
0100	SL			SHIFTS the binary value in the register to the left by one and places a zero in the LSB
0101	SR			SHIFTS the binary value in the register to the right by one and places a zero in the MSB
DATA TRANSFERS
0110	LD			LOADs the value from the memory address specified in the two instructions immediately following into the register.
0111	LACC			LOADs the value from the memory address specified in the two instructions immediately following into the accumulator
1000	SACC			SAVEs the value in the accumulator to the memory address specified in the two instructions immediately following.
CONTROL
1001	B			BRANCHes (jumps) to the instruction in the memory address specified in the two instructions immediately following.
MISC/HARDWARE
1010	NOP			NO OPERATION.
1011	IDLE			IDLE's the hardware until the INTERRUPT pin is driven high.