PLA

FUNCTIONAL DESCRIPTION

The PLA is control unit for the rest of the CPU. Depending on the inputs, it outputs the correct signals to make the CPU execute the desired operation. The PLA consists of 5 different states. Most operations are only one state, which translates into one cycle. The arithmetic operations such as add, subtract, shift left, and shift right, can all be done in one cycle. The operations that require more than one state are the memory and control operations. The multiple states are a result of the need for the CPU to load the 8-bit address after loading the instruction.

One interesting aspect of the PLA is the feedback loops, labels CONT0 and CONT1. These labels are used to decrease the number of states needed. For all the multiple state instructions such as LREG, LACC, and BR, the only difference in the signals the PLA sends out comes in the last state. This means that the intermediate states are the exactly the same. In order to reuse these states, then, the feed back loops CONT0 and CONT1 are used. The following table shows how CONT0 and CONT1 are determined.

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INSTRUCTION	CONT0	CONT1
LREG	0	0
LACC	0	1
SACC	1	0
BR	1	1

The three ALU outputs are also in need of clarification. The signals INST_ALU0-INST_ALU3 are all used to tell the ALU which operation to perform. They are explained in the following table.

INSTRUCTION	INST_ALU0	INST_ALU1	INST_ALU2
ADD	0	0	0
SUB	0	0	1
OR	0	1	0
AND	0	1	1
SL	1	0	0
SR	1	0	1

The attached IRSIM file for the PLA details the timing of the signals and gives a good picture of how the PLA communicates to the PC, registers, and ALU.

EXPLANATION OF I/O SIGNALS

INPUTS	DESCRIPTION
RESTART	Sets the PLA to state0 where the PLA resets the PC
DATA0-DATA3	These lines are used to input both instructions and data
INT	This is an INTERRUPT signal that takes the chip out of IDLE state
CONT0-CONT1	This is a feedback signal to help the PLA distinguish between instructions
READY	This is a signal from external memory informing the CPU that the data requested from memory is ready

OUTPUTS	DESCRIPTION
A_B	This signal goes to a multiplexer which chooses between an A or B register of the PC
INC_PC	This signal tells the PC to increment to the next address
SET20	This signal resets the PC to 0
LATCH_L	This signal latches in the lower half of an 8-bit address into register B of the PC
LATCH_H	This signal latches in the upper half of an 8-bit address into register B of the PC
DATA_IN2PC	This is a signal to the bus controller to send the DATA lines to the PC
EN_AREG	This signal latches the values currently on the inputs of register A
EN_ACCUM	This signal latches the values currently on the inputs of the accumulator
INST_ALU0	This signal is a control instruction to the ALU
INST_ALU1	This signal is a control instruction to the ALU
INST_ALU2	This signal is a control instruction to the ALU
LAT_PASS_ALU	This signal lets the ALU latch it's inputs and outputs correctly
SET_CONT0	This is a feedback signal to the PLA to tell it which instruction was read in
SET_CONT1	This is a feedback signal to the PLA to tell it which instruction was read in
CONT_LAT	This signal latches the feedback signals so they are not constantly changing
DATA_IN2AREG	This is a signal to the bus controller to send the DATA lines to register A
DATA_IN2ACCUM	This is a signal to the bus controller to send the DATA lines to register A
RD_WRT	This is an output signal to external memory to inform memory whether a read or write is going to be performed
DATA_OUT_ACCUM	This is a signal to the bus controller to let the accumulator write to the bus
REGB2PC	This is a signal that tells the PC to set its address to the value in register B

ISSUES

The main issue in creating the PLA was to make it as few states as possible. This way, minimal space was taken up by the PLA. The first PLA that was created provided an overabundance of signals, and did not use the timing of the CPU correctly. As a result, it had over 20 states and was entirely too large. Once the timing was worked out, the PLA was able to shrink to only 5 necessary states.