INPUT TO MEG

OUTPUTS: A_B INC_PC SET20 LATCH_L LATCH_H DATA_IN2PC EN_AREG EN_ACCUM INST_ALU0 INST_ALU1 INST_ALU2 LAT_PASS_ALU SET_CONT0 SET_CONT1 CONT_LAT DATA_IN2AREG DATA_IN2ACCUM RD_WRT DATA_OUT_ACCUM REGB2PC;

reset on RESTART to state0;

-- STATE0 IS THE RESTART STAGE

state0: case (RESTART)

0 => state0;

1 => state1 (SET20);

endcase => state0;

-- STATE1 TAKES CARE OF BOTH THE RESTART AND DECODE STAGE

state1: case (READY DATA0 DATA1 DATA2 DATA3)

0 ? ? ? ? => state1;

1 0 0 0 0 => state1 (LAT_PASS_ALU EN_ACCUM INC_PC);

1 0 0 0 1 => state1 (LAT_PASS_ALU EN_ACCUM INST_ALU0 INC_PC);

1 0 0 1 0 => state1 (LAT_PASS_ALU EN_ACCUM INST_ALU1 INC_PC);

1 0 0 1 1 => state1 (LAT_PASS_ALU EN_ACCUM INST_ALU0 INST_ALU1 INC_PC);

1 0 1 0 0 => state1 (LAT_PASS_ALU EN_ACCUM INST_ALU2 INC_PC);

1 0 1 0 1 => state1 (LAT_PASS_ALU EN_ACCUM INST_ALU0 INST_ALU2 INC_PC);

1 0 1 1 0 => state2 (INC_PC CONT_LAT);

1 0 1 1 1 => state2 (INC_PC SET_CONT0 CONT_LAT);

1 1 0 0 0 => state2 (INC_PC SET_CONT1 CONT_LAT);

1 1 0 0 1 => state2 (INC_PC SET_CONT0 SET_CONT1 CONT_LAT);

1 1 0 1 0 => state1 (INC_PC);

1 1 0 1 1 => state5;

endcase => state1;

-- STATE2 IS FOR OBTAINING THE LOWER 4-bits OF A LOAD/STORE/BRANCH ADDRESS RETRIEVAL

state2: case (READY)

0 => state2;

1 => state3 (DATA_IN2PC LATCH_L INC_PC);

endcase => state2;

-- STATE3 IS FOR OBTAINING THE UPPER 4-BITS OF A LOAD/STORE/BRANCH ADDRESS RETRIEVAL

state3: case (READY CONT0 CONT1)

0 0 ? => state3;

1 0 ? => state4 (DATA_IN2PC LATCH_H A_B);

1 1 0 => state4 (DATA_IN2PC LATCH_H A_B DATA_OUT_ACCUM RD_WRT);

1 1 1 => state1 (DATA_IN2PC LATCH_H REGB2PC A_B);

endcase => state2;

-- STATE4 LOADS THE DATA INTO THE APPROPRIATE REGISTERS

state4: case (READY CONT0 CONT1)

0 ? ? => state4;

1 0 0 => state1 (EN_AREG DATA_IN2AREG INC_PC);

1 0 1 => state1 (EN_ACCUM DATA_IN2ACCUM INC_PC);

1 1 0 => state1 (INC_PC);

endcase => state4;

-- STATE5 IS FOR THE IDLE CONTROL

state5: case (INT)

0 => state5;

1 => state1 (INC_PC);

endcase => state5;