However, even an 8-bit carry-lookahead adder would go beyond our chip real-estate limits, for reasons described in the following. Thus, we implemented two 4-bit carry-lookahead adders, connected in a serial fashion.
The carry-lookahead adder equations are as follows:
The logic shown below implements the carry-lookahead equations described
generator XORs the input bits together to determine if this bit
position propagates a previous carry. The result of the propagate
generator is used directly in generating the sum bits. The generate
generator ANDs input bits together in order to determine if this bit
position will generate a new carry. The standard XOR and AND gates
used are the same as in the boolean unit.
The sum generator XORs the carry-in calculated from the previous two
bits and the XOR (propagate) of the current two bits--hence the name
carry look-ahead adder.
The carry generator in the CLA takes as its inputs the propagate/generate
signals and generates a carry for the next bit. We then find the XOR of this
carry bit with the next propagate bit (AND of two input bits) to generate
the sum. The carry generator was broken up into bitwise carries to not only
economize on space, but to also illustrate the tendency of the carry block to
"blow up" as more bits are added. It is because of this that
carry-lookahead adders are limited to 4-bits and are subsequently placed
in sequence (connecting the final carry-out of the lower-order adder to
the carry-in of the higher-order adder) for larger
The logic shown below implements the carry-lookahead equations described above.