#
Carry Look-Ahead Adder

We chose the static carry-look ahead adder for a number of reasons
based on a balance between size and speed. The fastest design
implements a parallel structure, where each bit is calculated
simultaneously. We were unable to utilize this design because of our
chip real estate limitations. On the other hand, a serial adder is
characterized by one of the simplest transistor structures, but is
excruciatingly slow. We then examined the carry-look ahead adder,
which is faster than the serial adder because the carry bit is
calculated parallel to the XOR operation on the inputs bits. We had
the option of going with a dynamic carry structure or a static
structure. We decided to use a static structure to avoid timing
problems associated with dynamic clocked circuits and latching of
outputs for valid signals.
However, even an 8-bit carry-lookahead adder would go beyond
our chip real-estate limits, for reasons described
in the following. Thus, we implemented two 4-bit carry-lookahead
adders, connected in a serial fashion.

The carry-lookahead adder equations are as follows:

The carry-lookahead adder follows this block diagram:

The carry-lookahead adder consists of a propagate/generate
generator, a sum generator, and a carry generator. Since we use twos-complement arithmetic, the adder also doubles as a
subtractor; for the latter function, the B input to the adder must be
inverted, and the carry-in to the lower adder must be "1".

The propagate
generator XORs the input bits together to determine if this bit
position propagates a previous carry. The result of the propagate
generator is used directly in generating the sum bits. The generate
generator ANDs input bits together in order to determine if this bit
position will generate a new carry. The standard XOR and AND gates
used are the same as in the boolean unit.

### Sum Generator

The sum generator XORs the carry-in calculated from the previous two
bits and the XOR (propagate) of the current two bits--hence the name
carry look-ahead adder.

### Carry Generator

The carry generator in the CLA takes as its inputs the propagate/generate
signals and generates a carry for the next bit. We then find the XOR of this
carry bit with the next propagate bit (AND of two input bits) to generate
the sum. The carry generator was broken up into bitwise carries to not only
economize on space, but to also illustrate the tendency of the carry block to
"blow up" as more bits are added. It is because of this that
carry-lookahead adders are limited to 4-bits and are subsequently placed
in sequence (connecting the final carry-out of the lower-order adder to
the carry-in of the higher-order adder) for larger
input combinations.
The logic shown below implements the carry-lookahead equations described
above.