The shift register is comprised of two 8-bit latches that are used partly because of Karplas timing requirements. In this case however, the shift register latches were optimize for the multiply operation. One register takes as its input the output of the adder. This register stores the high order bits (in multiply operations), and is MUXed to the output pins when an "add" is desired. However, if a multiply operation is desired (which is simply adding and shifting), the lowest order bit from the high order register is rotated into the next available latch in the lower order register, and the "add" operation cycles. Seven control lines from the PLA control this operation. An additional opcode combination is provided for viewing the high order bits at the end of multiply, as the default output of the standard multiply operation is the value stored in the lower order register. See the section on serial multiply for additional information.