This page contains diagrams and explanations of the logic implemented in our ALU chip. Components of primary concern are the following:

• Carry Look-Ahead Adder
• Serial Multiplier
• Boolean Unit
• Shift Unit
• Control Unit
• Basic building blocks

CARRY LOOK-AHEAD ADDER

The carry look-ahead adder was chosen as an optimum balance between circuit real estate and speed. The current carry C_i is calculated by the following formula:

where:

The sum S_i is calculated by the following formula:

In the case that a negative number is added (i.e. 3 + (-6) = ?), the carry-in value is set to one. This is because in two's complement, negation is achieved by inverting bits and adding one (the carry-in). Otherwise, the carry-in value defaults to zero.

The following image provides a top-level look at the logic implemented in our adder.

We have also included the following logic and magic layouts of the adder subcomponents.

• Full Adder: magic
• Propagate Generator: logic, magic
• Carry Generator: logic, magic
• Sum Generator: logic, magic

SERIAL MULTIPLY

The algorithm used for multiplication is serial. The component takes two 8-bit numbers and performs multiplication in 8 clock cycles. Below is the block diagram detailing the process by which the multiply operation is performed.

• input A latched into a register; input B stored in shift register
• during first clock cycle, 8 bits of input A, i.e. a7 a6 a5 a4 a3 a2 a1 a0, ANDed with bit "b0"; generates first partial product
• product is sent to adder
• current value of temporary register (initially set to zero) added to partial product
• store LSB, least significant bit, of sum in output register
• remaining part of sum shifted by one bit to the right (zero goes to MSB, most significant bit); stored in temporary register
• during subsequent clock cycles, input A will be ANDed with bits b1 b2 b3 b4 b5 b6 b7, respectively
• for each clock cycle, the above operation is repeated, thus acquiring a single bit out of every iteration
• at end of eighth cycle, we have obtained 8 bits of the result; remaining 8 bits can be read from output register
  

• Full Multiply: magic
• 8-Bit Latch: magic
• Shift Register: magic

BOOLEAN UNIT

The above diagram shows the pattern for each bit of the Boolean unit; the unit as a whole is "embarassingly replicated". That is, each bit of the unit's output is dependent only on the corresponding bit of the inputs to the unit. The BSEL inputs (generated by the control block) determine which of the Boolean outputs to consider active in a given cycle.

We have also included the following magic layouts of the boolean subcomponents.

• 8-Bit AND Gate: magic
• 8-Bit OR Gates: magic
• 8-Bit NOT Gates: magic
• 8-Bit XOR Gates: magic
• Logic units:magic

Last Updated: December 13, 1996