SPANKy ISA

SPANKy!

Brought to you by group GAMMA:
Victoria Smith (vics@rice.edu)
Mara Prandi-Abrams (mabrams@rice.edu)
Dennis Geels (geels@rice.edu)

Overview - Functional Specifications - ISA - Controller - Design and Layout - Performance Analysis - Summary

423 Final Report

ISA

A SPANKy opcode consumes the first four bits of each opcode. The bit encoding and semantics of the instructions follow.
The next four bits denote the destination register, which is also a source operand in any I-FORM or store instruction (excluding HALT).
The second byte either denotes two source registers or contains a single eight-bit immediate value, depending on the instruction format.
Here are the two formats, with labelled bit ranges:

`BITS`	`0-3`	`4-7`	`8-11`	`12-15`
`S-FORM`	`OP`	`RD`	`RX`	`RY`
`I-FORM`	`OP`	`RD`	`IMM`

Here are SPANKy's instructions, with opcode bit encoding, assembly mnemonic, and semantics (in C-like syntax):

BITS	MNEMONIC	FORM	SEMANTICS
`0000`	`AND`	`S`	`RD = RX & RY`
`0001`	`ANDi`	`I`	`RD &= IMM`
`0010`	`OR`	`S`	`RD = RX \| RY`
`0011`	`ORi`	`I`	`RD \|= IMM`
`0100`	`NOT`	`S`	`RD = !RX`
`0101`	`NOTi`	`I`	`RD = !IMM`
`0110`	`ROTL`	`S`	`RD = RY << RX`
`0111`	`ROTLi`	`I`	`RD <<= IMM`
`1000`	`ADD`	`S`	`RD = RX + RY`
`1001`	`ADDi`	`I`	`RD += IMM`
`1010`	`LD`	`S`	`RD = MEM(RX)`
`1011`	`LDi`	`I`	`RD = MEM(IMM)`
`1100`	`ST`	`S`	`MEM(RX) = RD`
`1101`	`STi`	`I`	`MEM(IMM) = RD`
`1110`	`BZ`	`I`	`PC = IMM if (RD == 0)`
`1111`	`HALT`	`I`	`SPANKy stops.`

SPANKy also provides a few useful pseudo-ops for your chewing enjoyment:

PSEUDO-OP	IMPLEMENTATION
`NOP`	`AND R0,R0,R0`
`CLR RX`	`ANDi RX,0`
`MOV RD,RS`	`OR RD,RS,RS`
`SET RX,IMM`	`CLR RX ORi RX,IMM`
`SUB RD,RX,RY`	`NOT RY,RY ADDi RY,1 ADD RD,RX,RY`