Multiply Program Testing

In the test vectors below, the specific numbers to multiply are 3 and 2.

Program Code:

0  SETMI 1010
1  LDI   1010
2  LW    0011  // reg0 <= value at mem address AA
3  SETMI 0101
4  LDI   0101
5  LW    1011  // reg2 <= value at mem address 55

6  LDI   0001
7  SETMI 0001
8  BEZ   1011  // if $reg2 = 0, goto done

9  ZERO  0100  // reg1 <= 0
10 SETMI 0000 

loop: 
11 LDI   0001
12 SUB   1011  // decrement reg2
13 ADD   0100  // reg1 <= $reg1 + $reg0, reg1 is like an accumulator
14 LDI   1011
15 BGZ   1011  // if $reg2 is still greater than 0 loop

done:
16 ZERO  1000  // reg2 <= 0
17 SW    0110  // store product at mem address 00

logfile cpu.log

clock CLKA     0 1 0 0
clock CLKB     0 0 0 1

| pin vectors
vector MemData MemData<7> MemData<6> MemData<5> MemData<4> MemData<3> MemData<2> MemData<1> MemData<0>
vector MemAdd  MemAdd<8> MemAdd<7> MemAdd<6> MemAdd<5> MemAdd<4> MemAdd<3> MemAdd<2> MemAdd<1> MemAdd<0>
vector State   StBit0 StBit1
vector RdReg1 RegA<3> RegA<2> RegA<1> RegA<0>
vector RdReg2<3-2> RegB<3> RegB<2>
vector ALU ALU<3> ALU<2> ALU<1> ALU<0>

| core vectors
vector PostMemData PostMemData<7> PostMemData<6> PostMemData<5> PostMemData<4> PostMemData<3> PostMemData<2> PostMemData<1> PostMemData<0>
vector PC PC<7> PC<6> PC<5> PC<4> PC<3> PC<2> PC<1> PC<0>
vector SelectedPC SelectedPC<7> SelectedPC<6> SelectedPC<5> SelectedPC<4> SelectedPC<3> SelectedPC<2> SelectedPC<1> SelectedPC<0>
vector PCin PCin<7> PCin<6> PCin<5> PCin<4> PCin<3> PCin<2> PCin<1> PCin<0>
vector PInF PInF<7> PInF<6> PInF<5> PInF<4> PInF<3> PInF<2> PInF<1> PInF<0>
vector Add1in Add1in<7> Add1in<6> Add1in<5> Add1in<4> Add1in<3> Add1in<2> Add1in<1> Add1in<0>
vector PAdd1 PAdd1<7> PAdd1<6> PAdd1<5> PAdd1<4> PAdd1<3> PAdd1<2> PAdd1<1> PAdd1<0>
vector incPC incPC<7> incPC<6> incPC<5> incPC<4> incPC<3> incPC<2> incPC<1> incPC<0>
vector PMRS PMRS<3> PMRS<2> PMRS<1> PMRS<0>
vector MemReg RMDATA<3> RMDATA<2> RMDATA<1> RMDATA<0>
vector intRegA intRegA<3> intRegA<2> intRegA<1> intRegA<0>
vector RdReg2 intRegB<3> intRegB<2> intRegB<1> intRegB<0>
vector PID PID<3> PID<2> PID<1> PID<0>
vector PM2R PM2R<3> PM2R<2> PM2R<1> PM2R<0>
vector MImm MImm<3> MImm<2> MImm<1> MImm<0>
vector P4I P4I<3> P4I<2> P4I<1> P4I<0>
vector PSrc2 PSrc2<3> PSrc2<2> PSrc2<1> PSrc2<0>
vector PALU PALU<3> PALU<2> PALU<1> PALU<0>
vector WBData WBData<3> WBData<2> WBData<1> WBData<0>
vector PIR3 PIR3<1> PIR3<0>
vector intState intStBit0 intStBit1
vector Ins Ins<7> Ins<6> Ins<5> Ins<4> Ins<3> Ins<2> Ins<1> Ins<0>

| pin ana's
ana CLKA CLKB Restart State MemWriteQbar OEbar MemData MemAdd ALU RdReg1 RdReg2 RdReg2<3-2> MemReg

|ana intRestart
|ana PostMemData
ana Ins
|ana InF
|ana intState
|ana ClearRegs
|ana ImpReg3
|ana FourImm
|ana ALUSrc2
|ana RegWrite
|ana Mem2Reg
|ana ImmData
|ana Branch
|ana SetPC
|ana RegRead
|ana PCstore
|ana PCstorebar
ana PC
|ana Add1in
|ana EQZ GTZ
|ana PBZ
|ana PCSelect
|ana PCin
|ana PInF
|ana PAdd1
|ana incPC
|ana SelectedPC
|ana PCin
|ana PMRS
ana MemReg
|ana PALU
|ana WBData
|ana MImm
|ana PM2R
|ana PIR3
|ana intRegA
ana RdReg2
|ana PID
|ana PM2R
|ana MImm
|ana P4I
|ana PSrc2
|ana PALU
|ana WBData
|ana PIR3
|ana Vdd
|ana GND


V RESTART       1 0 0 0 0 0 0 0 0 0 0 0 0 0  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  0  0 0 0
0 0 0 0 0 0  0 0 0 0 0 0 0 0 0 0
V  MemData HIZ HIZ SETMI1010 HIZ LDI1010 HIZ LW0011 00000010 HIZ  SETMI0101 HIZ LDI0101 HIZ LW1011 00000011 HIZ LDI0001 HIZ SETMI0001 HIZ BEZ1011 H
IZ ZERO0100 HIZ SETMI0000 HIZ LDI0001 HIZ SUB1011 HIZ HIZ ADDD0100 HIZ HIZ LDI1011 HIZ BGZ1011 HIZ LDI0001 HIZ SUB1011 HIZ HIZ ADDD0100 HIZ HIZ LDI
1011 HIZ BGZ1011 HIZ LDI0001 HIZ SUB1011 HIZ HIZ ADDD0100 HIZ HIZ LDI1011 HIZ BGZ1011 HIZ ZERO1000 HIZ SW0110 HIZ NOOP NOOP NOOP NOOP
R