JAWs CPU - Cell Hierarchy

Click on a cell to see magic layout and IRSIM test results for that cell. Note: subcells are listed below the cells in which they appear. Many cells may appear more than once in this list.

JAWs CPU

• Pad Frame (40p2200)

• Register File (regfile)
  • 4-bit register (reg)
    • 1-bit Latch (n_latch)
      • 2-input NOR (2nor)
      • Inverter (invert)
    • Inverter (inverter_1input)
    • 3-input NAND (3nand)
  • 4-input, 4-bit mux (regfilemux)
    • 4-bit Transmission Gate (4b_decoded_tgate)
      • 1-bit Transmission Gate (tgate)
      • 3-input NAND (3nand)
      • Inverter (inverter_1input)
  • Inverter (invert, inverter_1input)
  • 2-input NAND (2nand)
  • 2-input NOR (2nor)

• ALU (ALU)
  • 2-input, 4-bit mux (2mux4bus)
    • 2-input, 1-bit mux (2muxnoc)
  • 2-to-4 decoder (2to4_decoder)
    • 2-input NAND, 4-bits (2nand_4bits)
      • 2-input NAND (2nand)
    • 4-bit Inverter (invert_4bits)
      • Inverter (invert)
    • Inverter (invert)
  • 4-bit Shift Register (4b_shift_contacts)
    • 1-bit shift unit (shift_1cell_contacts)
  • Manchester Adder (4b_man)
    • Manchester Adder cell (man_add)
      • PG Generator (pg)
        • 2-input NAND (2nand)
        • Inverter (inverter_1input)
      • 2-input XOR (n_xor)
      • Inverter (inverter_1input)
  • 4-bit Transmission Gate (4b_decoded_tgate)
    • 1-bit Transmission Gate (tgate)
    • 3-input NAND (3nand)
    • Inverter (inverter_1input)
  • 4-bit Transmission Gate (4b_tgate)
    • 1-bit Transmission Gate (tgate)
    • Inverter (inverter_1input)
  • 2-input NOR, 4-bits (2nor_4bits)
    • 2-input NOR (2nor)
  • 2-input NAND, 4-bits (2nand_4bits)
    • 2-input NAND (2nand)
  • 4-bit Inverter (invert_4bits)
    • Inverter (invert)
  • Inverter (invert)

• PLA (controlpla)

• Add-one Unit (add_1_new)
  • 2-bit Add-one cell (add_1_2units)
    • 1-bit Add-one cell (add_1_unit)
      • 2-input XOR (xor)
      • Inverter (inverter_1input)
      • 2-input NOR (2nor)
    • 1-bit Add-one cell (add_1_unit_mirror)
      • 2-input XOR (xor)
      • Inverter (inverter_1input)
      • 2-input NOR (2nor)

• 1-bit latch (latch)
  • 2-input NOR (2nor)

• 4-bit Latch - protected (n_latch4bus)
  • 1-bit Latch (n_latch)
    • 2-input NOR (2nor)
    • Inverter (invert)

• 4-bit Latch - not protected (latch4bus)
  • 1-bit Latch (latch)
    • 2-input NOR (2nor)

• 8-bit Latch - protected (n_latch8bus)
  • 1-bit Latch (n_latch)
    • 2-input NOR (2nor)
    • Inverter (invert)

• 8-bit Latch - not protected (latch8bus)
  • 1-bit Latch (latch)
    • 2-input NOR (2nor)

• 2-input NAND (2nand)

• 2-input NOR (2nor)

• 4-input NOR (4nor)

• Inverter (invert)

• 2-input, 1-bit mux (2mux)

• 2-input, 2-bit mux (2mux2bus)
  • 2-input, 1-bit mux (2muxnoc)

• 2-input, 4-bit mux (2mux4bus)
  • 2-input, 1-bit mux (2muxnoc)

• 2-input, 8-bit mux (2mux8bus)
  • 2-input, 1-bit mux (2muxnoc)

• 2-input, 9-bit mux (2mux9bus)
  • 2-input, 1-bit mux (2muxnoc)

• 4-bit Greater than zero detect (gt_zero)
  • 2-input NOR (2nor)
  • 3-input NOR (3nor)

Back to JAWs Final Report.