This test is designed to verify that all bits are passed to the Instruction Fetch Mux correctly. We ensure that the InfMux works by writing 05 to data address 55 and by writing 0a to data address aa.
To verify functionality, we looked at the data and address provided by the chip on both of the SW operations. We also watched the PC, and made sure that the register file provided correct values for each instruction.
Chips 2, 4, and 5 all passed this test with complete functionality.
Instruction Sequence:
Restart of the chip ...
SETMI 1010
LDI 1010
BEZ 0011
SW 1111
SETMI 0101
LDI 0101
BEZ 0011
SW 1111
NOOP
| SRAM Test logfile cpu.log clock Vdd 1 1 1 1 clock CLKA 0 1 0 0 clock CLKB 0 0 0 1 | pin vectors vector MemData MemData7 MemData6 MemData5 MemData4 MemData3 MemData2 MemData1 MemData0 vector iMemData iMemData7 iMemData6 iMemData5 iMemData4 iMemData3 iMemData2 iMemData1 iMemData0 vector MemAdd MemAdd8 MemAdd7 MemAdd6 MemAdd5 MemAdd4 MemAdd3 MemAdd2 MemAdd1 MemAdd0 vector iMemAdd iMemAdd8 iMemAdd7 iMemAdd6 iMemAdd5 iMemAdd4 iMemAdd3 iMemAdd2 iMemAdd1 iMemAdd0 vector State StBit0 StBit1 vector RdReg1 RegA3 RegA2 RegA1 RegA0 vector RdReg232 RegB3 RegB2 vector ALU ALU3 ALU2 ALU1 ALU0 | pin ana's ana CLKA CLKB Restart MemAdd State MemWriteQbar OEbar MemData RdReg232 ana RdReg1 ALU Vdd ana Trigger ana ILOAD WE_L iMemData |ana iMemAdd <- not enough room on analyzer pins V RESTART 0 V iMemAdd 000000000 000000000 000000000 000000001 000000001 000000001 000000010 000000010 000000010 010101010 010101010 010101010 V ILOAD 0 V ILOAD_bar 1 V WE_L 1 0 1 1 0 1 1 0 1 1 0 1 V iMemData 10001010 10001010 10001010 11001010 11001010 11001010 10100011 10100011 10100011 10011111 10011111 10011111 R V iMemAdd 010101011 010101011 010101011 010101100 010101100 010101100 010101101 010101101 010101101 001010101 001010101 001010101 V iMemData 10000101 10000101 10000101 11000101 11000101 11000101 10100011 10100011 10100011 10011111 10011111 10011111 R V RESTART 0 0 0 0 0 0 0 0 0 1 0 0 V ILOAD 0 0 0 0 0 0 0 1 1 1 1 1 V ILOAD_bar 1 1 1 1 1 1 1 0 0 0 0 0 V WE_L 1 0 1 1 0 1 1 1 1 1 1 1 V iMemAdd 001010110 001010110 001010110 001010110 001010110 001010110 111111111 111111111 111111111 111111111 111111111 111111111 V iMemData 00000000 00000000 00000000 00000000 00000000 00000000 11111111 11111111 11111111 11111111 11111111 11111111 R V ILOAD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 V ILOAD_bar 0 V WE_L 1 V iMemAdd 111111111 V iMemData 11111111 V RESTART 0 R