This test was meant to provide more thorough analysis of ALU operations not covered by some of our other tests. To verify our results, we first looked at the 5 SW operations performed by the program. Each SW reflects some results of our ALU operations. By verifying that we were writing the correct data to the correct memory address, we conclude that the ALU operations were performed correctly. We also verified the PC value throughout the program.
Chips 2, 4, and 5 all passed this test with complete functionality. Chip 1 FAILED this test (see Failure Analysis).
Instruction Sequence:
Restart of the chip ...
LDI1111
ADDD0011
ADDD0011
SW0001
LDI0011
AND0011
SW0001
SUB0011
SW0001
NOT0000
SW0001
NOT0011
SW1100
NOOP
| SRAM Test logfile cpu.log clock Vdd 1 1 1 1 clock CLKA 0 1 0 0 clock CLKB 0 0 0 1 | pin vectors vector MemData MemData7 MemData6 MemData5 MemData4 MemData3 MemData2 MemData1 MemData0 vector iMemData iMemData7 iMemData6 iMemData5 iMemData4 iMemData3 iMemData2 iMemData1 iMemData0 vector MemAdd MemAdd8 MemAdd7 MemAdd6 MemAdd5 MemAdd4 MemAdd3 MemAdd2 MemAdd1 MemAdd0 vector iMemAdd iMemAdd8 iMemAdd7 iMemAdd6 iMemAdd5 iMemAdd4 iMemAdd3 iMemAdd2 iMemAdd1 iMemAdd0 vector State StBit0 StBit1 vector RdReg1 RegA3 RegA2 RegA1 RegA0 vector RdReg232 RegB3 RegB2 vector ALU ALU3 ALU2 ALU1 ALU0 | pin ana's ana CLKA CLKB Restart MemAdd State MemWriteQbar OEbar MemData RdReg232 ana RdReg1 ALU Vdd ana Trigger ana ILOAD WE_L iMemData |ana iMemAdd <- not enough room on analyzer pins V RESTART 0 V iMemAdd 000000000 000000000 000000000 000000001 000000001 000000001 000000010 000000010 000000010 000000011 000000011 000000011 V ILOAD 0 V ILOAD_bar 1 V WE_L 1 0 1 1 0 1 1 0 1 1 0 1 V iMemData 11001111 11001111 11001111 01010011 01010011 01010011 01010011 01010011 10010001 10010001 10010001 R V iMemAdd 000000100 000000100 000000100 000000101 000000101 000000101 000000110 000000110 000000110 000000111 000000111 000000111 V iMemData 11000011 11000011 11000011 00100011 00100011 00100011 10010001 10010001 10010001 00010011 00010011 00010011 R V iMemAdd 000001000 000001000 000001000 000001001 000001001 000001001 000001010 000001010 000001010 000001011 000001011 000001011 V iMemData 10010001 10010001 01100001 01100000 01100000 01100000 10010001 10010001 10010001 01100011 01100011 01100011 R V RESTART 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 V ILOAD 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 V ILOAD_bar 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 V WE_L 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 V iMemAdd 000001100 000001100 000001100 000001101 000001101 000001101 111111111 111111111 111111111 111111111 111111111 111111111 111111111 111111111 111111111 V iMemData 10011100 10011100 10011100 00000000 00000000 00000000 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 R V ILOAD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 V ILOAD_bar 0 V WE_L 1 V iMemAdd 111111111 V iMemData 11111111 V RESTART 0 R