Testing Methodology - JAWs CPU

Hardware Setup

Our basic setup consisted of the stimulus, SRAM, analyzer, CPU, 7 SN74S241 Octal Buffers, and 1 NAND chip. The stimulus provided loading of instructions into the SRAM as well as clocks and RESTART for the CPU. The tri-stateable buffers separated the CPU memory signals from the stimulus memory signals when the instructions were being loaded into the SRAM. The enables for the buffers, ILOAD and /ILOAD, are switched after the instructions are loaded into memory, so that the CPU can begin operating. The use of the analyzer is clearly shown in the diagram below. The NAND chip is necessary to prevent fighting between the loop of buffers that separate the bidirectional memory data lines of the CPU from the memory data lines of the stimulus. Since both buffers in the loop could be driving values before the instruction loading is finished, one cannot turn one of the buffers on while the other is on. So after instruction loading is done, we can never turn both buffers on to effectively create a wire between the SRAM and CPU because there is never any assurance that the enables on the buffers can switch at exactly the same time. Thus, our NAND gates are wired as to provide the control for using the lines for two-way communication.

We used six sets of test vectors which tried to exploit possible stuck-at faults as well as functionality flaws. We basically sent every possible logic value across every possible data path to ensure that our chips were internally working well (Note that A's and 5's are used heavily to test this in as few instructions as possible). These types of tests display the correctness of our chip to a high degree because we have a great deal of observability at the pins (registers, ALU outputs, memory data, memory address, and state bits). These six sets of test vectors each had about ten or more instructions each. They covered all instructions.

Since some aspects of our design, like the ALU and PC, we could not reasonably test exhaustively, we used three programs which ran from 30-40 instructions each to gain a better confidence level in our chip and its robustness.

Functional Block Correctness

Register File: All 16 latches (4 4-bit registers) were written to and read from in the aforementioned test vectors.
ALU: Since we could not reasonably test the ALU exhaustively, we tested all operations with a good sampling of operands. Our 30-40 instruction programs tested the ALU in a solid manner.
Memory Interface: The memory interface was untested during our simulations last semester, so this functionality was very important to us. The interface worked completely. This was indirectly tested through every test vector because all instructions must use the memory interface.
Program Counter: We could not reasonably test the program counter exhaustively, so we relied on our numerous branching vector sets to verify the program counter. Also the correct operation of our longer programs verified the correctness of the less significant bits in our program counter.
Data Paths and Control: By propagating all possible logic values across all the important bus lines (as mentioned above), we demonstrate correct data paths and control.
State Machine Controller: Our state machine has only four states, and its correct operation in all states for all instructions is easily inferred from the tests indicate above.

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Testing Methodology - JAWs CPU

Hardware Setup

Test Vector Overview