FAQs:
Check out the explanations of all the extraction options. You can also read about Diva verification (DRC, extraction, and LVS) in general.
The extractor should automatically extract a ``designed'' capacitor, as long as it meets one of the following criteria:
cap_id marker layer (i.e. a
rectangle on the cap_id layer completely overlaps the
rectangles that make up the capacitor) There are three quick things to check:
Extract_parasitic_caps switch in the
Extract form is on. (Click the "Set Switches" button, then click on
Extract_parasitic_caps.)
NCSU_parasiticCapIgnoreThreshold = 10e-15 in the
CIW. (The default value for this variable is set in
skill/globalData.il.)
Check these things:
Also, keep in mind that the CDK does not (yet) currently support extraction of parasitic resistors.
Using the CDK extract rules, Diva will extract only the following structures as resistors:
Generically, your resistor should look something like this:
This layout shows a poly/sblock resistor. Although this example shows a single straight length of poly inside the sblock rectangle, it's OK if there are bends (i.e. serpentine resistors are fine) - the extractor applies a correction factor to the resistance value at the corners of the bends. However, note that the contacts must be outside the res_id/sblock/highres rectangle.
For the purposes of calculating resistance, only the poly/elec/nwell inside the res_id/sblock/highres rectangle is considered. For example, in the above figure, the resistance is calculated using a length of 4.2 microns and a width of 1.2 microns (i.e., 3.5 squares).
FYI, sblock and highres are ``mask'' layers that get turned into real physical masks. The res_id layer, on the other hand, is simply a ``convenience'' layer that tells Diva that you intend the poly/elec/nwell underneath it to be a resistor.
If you're working in a design library that was created before 0.99.6
was installed, the layer property sheetResistance (defined
in techfile/layerDefinitions.tf), which is used to calculate
the resistor value, almost certainly doesn't exist. See the doc on resistor
extraction for instructions on how to add the required properties to
your technology library.
In the LVS form, make sure the rules file and rules library are filled in with the name divaLVS.rul and the name of your technology library, respectively. (This should be handled automatically, but check just in case.) Otherwise Diva might not be applying all the appropriate LVS rules it should be. (Note that if you've modified the LVS rules using the ``NCSU->Modify LVS Rules...'' form, the LVS form will have your design library name in the rules library field. This is OK.)
You probably need to set the shell environment variable
CDS_Netlisting_Mode to Analog. For
csh or tcsh, type setenv CDS_Netlisting_Mode
Analog in the shell window before starting Cadence.
You usually see this in a schematic which contains three-terminal MOS symbols ([np]mos from NCSU_Analog_Parts) but has neither any digital gates (from NCSU_Digital_Parts) nor vdd!/gnd! nets. By default, the three terminal MOS devices have their bulk nodes connected to ``vdd!'' (pmos) or ``gnd!'' (nmos), so if the netlister can't find a net by that name it's going to complain. The digital gates already include vdd!/gnd! nets, which is why you don't see this error in a schematic which has any gate instances.
The simplest solution is to instantiate vdd! and gnd! symbols (from the Supply_Nets category of NCSU_Analog_Parts) in your schematic. You don't have to connect them to anything; the point is just to make nets with the required names.
Alternatively, you can change the bulk node connection directly. Edit the transistor properties (select the transistor and hit q) and simply type the desired net name in the ``Bulk node connection'' field.
Probably because you didn't tell it to check for transistor size mismatches. Select the ``NCSU->Modify LVS Rules...'' menu entry and check the ``Compare FET parameters'' check box if you want LVS to warn you of size mismatches. Take a look at all the LVS options you can set.
Diva creates lots of temporary files (by default in the current
directory) and if it runs out of space it can fail. You can tell Diva
where to store these files by setting the environment variable
DRCTEMPDIR before starting Cadence. The (csh) syntax is
setenv DRCTEMPDIR "dir1 [dir2] [dir3] [...]". The temp
files are then stored in these directories.
The NCSU CDK is © NC State University, 1998-2000. Users are free to use or modify the NCSU CDK as appropriate as long as this notice appears in it. You are also advised that you use the NCSU CDK at your own risk. By using the NCSU CDK, you assume all liability for any resulting errors and problems.