Brandon and Patrick's Project

Friday
03/29/2024

Index
Introduction
Abstract
Background
Procedure
Design Details
Finite Register Effects
Data Analysis
Conclusion
Source Files
Our Group

Hits
Hits
Design Details

The codec provides a high quality digital-to-analog converter (DAC) and analog-to-digital converter (ADC) for our input and ou

The codec provides a high quality digital-to-analog converter (DAC) and analog-to-digital converter (ADC) for our input and output signals.  Oversampling sigma-delta technology is used, enabling high resolution A/D and D/A conversion at a relatively low cost. The codec consists of a pair of 16-bit synchronous serial conversion paths (one for input and one for output) and includes an interpolation filter before the DAC and a decimation filter after the ADC. Other overhead functions provided by the codec include timing (sample rate, FSD delay) and control (programmable gain amplifier, PLL, communication protocol, etc.).  The Multichannel Buffered Serial Port (McBSP) is used as a serial port interface for receiving and transmitting data. 

 

Our code is used to operate the code in two distinct phases.  In the “standard execution stage”, we are operating on a data buffer – calculating the fft, applying a filter or calculating an ifft.  Whenever a data sample is received, however, the McBSP interrupts to the CPU.  Upon the activation of the interrupt, the current state of the processor is saved and execution of the interrupt service routine (ISR) begins.  During the ISR, the received sample is put in the receive buffer and a sample is transmitted from the transmit buffer.  Both of these samples use the McBSP as their data-path.  Upon completing this action, the ISR terminates and the processor is restored to its pre-interrupt state.  It then continues in the “standard execution” stage until the McBSP again interrupts to the CPU. 

 

In designing our program, we had to deal with several hardware issues and limitations, including:

1.                        Limited sampling rate of codec (16 kHz)

2.                        Fixed point processor requires use of Q15 data type

3.                        Amount of onboard memory limits buffer size

4.                        CPU speed limits number of available instructions between interrupts

Clipping occurs at high input signal volumes

Any comments or questions? Please email us at bessig@rice.edu or pecresap@rice.edu.
Last updated on December 16, 2000.