PLA Description - JAWs CPU

Most of our instructions can be characterized by an Instruction Fetch state and a Register Read state. The ALU instructions also have a Write Back state for register writes. At startup (when Restart is asserted), we have one state which is used for clearing all registers. Some instructions are 2 states, while some use 3. Since we are not using pipelining, it is to our benefit to use the least amount of states per instruction.

INPUTS: RESTART OP3 OP2 OP1 OP0;
OUTPUTS: SetRM MRegSrc SetPC Branch MemRead MemWrite InF 
    Mem2Reg ImmData ImpReg3 RegWrite RegRead WriteZero 
    ClearRegs ALUSrc2 FourImm;

--  Definitions
#define OPCODE 	OP3 OP2 OP1 OP0
#define NOP	0 0 0 0
#define SUB     0 0 0 1
#define AND     0 0 1 0
#define OR      0 0 1 1
#define ADDI    0 1 0 0
#define ADDD    0 1 0 1
#define NOT     0 1 1 0
#define SLL     0 1 1 1
#define SETMI   1 0 0 0
#define SW      1 0 0 1
#define BRANCH  1 0 1 ?
#define LDI     1 1 0 0
#define LW      1 1 0 1
#define SETM    1 1 1 0
#define ZERO    1 1 1 1

reset on RESTART to Start(ClearRegs);

Start: 	GOTO InstFetch(InF MemRead);

InstFetch:  case (OPCODE)
		NOP	=> WriteBack(SetPC);
		ADDD	=> RegReadALUEx(SetPC RegRead);
		SUB	=> RegReadALUEx(SetPC RegRead);
		NOT	=> RegReadALUEx(SetPC RegRead);
		AND	=> RegReadALUEx(SetPC RegRead);
		OR	=> RegReadALUEx(SetPC RegRead);
		ADDI	=> RegReadALUEx(SetPC RegRead ImpReg3 FourImm ALUSrc2);
		SLL	=> RegReadALUEx(SetPC RegRead ALUSrc2);
		LW	=> RegReadALUEx(SetPC RegRead MemRead);
		SW	=> RegReadALUEx(SetPC RegRead MemWrite);
		SETM	=> RegReadALUEx(SetPC RegRead SetRM MRegSrc);
		SETMI	=> RegReadALUEx(SetPC SetRM);
		BRANCH  => RegReadALUEx(SetPC RegRead Branch);
		LDI	=> WriteBack(SetPC RegWrite ImpReg3 ImmData);
		ZERO	=> WriteBack(SetPC RegWrite WriteZero);
	endcase => ANY;

RegReadALUEx: case (OPCODE)
		ADDD	=> WriteBack(RegWrite);
		SUB	=> WriteBack(RegWrite);
		NOT	=> WriteBack(RegWrite);
		AND	=> WriteBack(RegWrite);
		OR	=> WriteBack(RegWrite);
		ADDI	=> WriteBack(RegWrite ImpReg3);
		SLL	=> WriteBack(RegWrite);
		LW	=> WriteBack(RegWrite Mem2Reg);
		SW	=> InstFetch(InF MemRead);
		SETM	=> InstFetch(InF MemRead);
		SETMI	=> InstFetch(InF MemRead);
		BRANCH	=> InstFetch(InF MemRead);
	endcase => ANY;

WriteBack: GOTO InstFetch(InF MemRead);