Index of /elec522/w9

	Name	Last modified	Size	Description
	Parent Directory		-
	fpga_timing_ex.pdf	2001-03-17 12:56	819K
	virtuoso_layout/	2002-03-22 00:00	-
	doc/	2002-03-14 09:54	-

This is the toplevel directory of the North Carolina State University Cadence Design Kit for full-custom IC fabrication through MOSIS.

Please take a moment to look over the release notes, especially if you are upgrading from a previous release!

The CDK includes documentation for users and admins.

You also might be interested in checking out the NCSU Cadence Web site, or you can go directly to the CDK home page.

Email us your questions, comments and suggestions!

And last but not least, we'd like to say thanks to everyone who has contributed to the CDK.

Overview

The NCSU CDK focuses on providing the means to do full-custom CMOS IC design through MOSIS, including schematic entry, Verilog digital simulation, analog circuit simulation, layout DRC checking and device extraction, and mask generation. It supports 4.4 and is not backward compatible with 4.3.x. All SKILL code is available as source.

The tools used in the kit are Virtuoso, Composer, Analog Artist, Virtuoso-XL and Diva.

What it is...

In particular, the kit features:

• support for all MOSIS processes which support the SCMOS rules, including process-dependent layers, e.g., pbase for NPNs

• layermaps for MOSIS CIF/GDSII import/export

• Diva verification: DRC (all rules from the MOSIS SCMOS User's Manual 7.4), extraction (MOSFETs, high-voltage MOSFETs, cwell/{m1,elec,polycap}-poly/inter-metal/parasitic capacitors, vertical NPN BJTs, diodes, resistors), and LVS

• Composer with interface to

  • HSPICE/Spectre through Analog Artist, with MOSIS-provided transistor models in place
  • Verilog with technology-independent parts
  
  

• technology-independent libraries for analog (eg, RLC, transistors) and digital (eg, gates) parts. These parts have SKILL code hooked in to enforce sizing and grid rules (eg, minimum width/length, half-lambda grid), automatic transistor model selection depending on technology, and drain/source area/perimeter estimation.

• technology libraries (ie, one library for every MOSIS SCMOS process) with parameterized layout cells setup for both manual use and layout synthesis via Virtuoso-XL.

• MOSIS wirebond pads (HP 0.4um, 0.6um; AMI 0.6um, 1.2um; TSMC 0.40um)

• various user-friendly GUI enhancements

  • simplified library creation and technology file attachment for MOSIS technologies
  • users can easily create their own menus with simple text file descriptions
  • click on any object to print info about it in the CIW
  • enhanced label creation (Virtuoso)
  • align layout objects (Virtuoso)
  • Perl/Tk program to easily convert 1's and 0's into SPICE pwl and pulse sources,
  • insert likeness of JPEG images into layout (Virtuoso), (useful for signing, or putting drawings or photos on, chips)
  • create a ``publication-quality'' schematic from a working schematic
  • import text strings to layout (Virtuoso)
  
  

• documentation of all customizations in either HTML or OpenBook format

and what it doesn't...

A few things that the kit doesn't do:

• P & R
• provide a standard cell layout library
• digital timing analysis
• parasitic resistance extraction

The NCSU CDK is ŠNC State University, 1998, 1999, 2000. Users are free to use or modify the NCSU CDK as appropriate as long as this notice appears in it. You are also advised that you use the NCSU CDK at your own risk. By using the NCSU CDK, you assume all liability for any resulting errors and problems.