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roneos
Operating System for the r-one robot
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Macros | |
#define | NRF_ENAA_ENAA_P5 5 |
#define | NRF_ENAA_ENAA_P4 4 |
#define | NRF_ENAA_ENAA_P3 3 |
#define | NRF_ENAA_ENAA_P2 2 |
#define | NRF_ENAA_ENAA_P1 1 |
#define | NRF_ENAA_ENAA_P0 0 |
#define | NRF_DYNPD_DPL_P5 5 |
#define | NRF_DYNPD_DPL_P4 4 |
#define | NRF_DYNPD_DPL_P3 3 |
#define | NRF_DYNPD_DPL_P2 2 |
#define | NRF_DYNPD_DPL_P1 1 |
#define | NRF_DYNPD_DPL_P0 0 |
#define | NRF_FEATURE_EN_DPL 2 |
#define | NRF_FEATURE_EN_ACK_PAY 1 |
#define | NRF_FEATURE_EN_DYN_ACK 0 |
- Instruction Set - | |
#define | NRF_R_REGISTER 0x00 |
#define | NRF_W_REGISTER 0x20 |
#define | REGISTER_MASK 0x1F |
#define | NRF_R_RX_PAYLOAD 0x61 |
#define | NRF_W_TX_PAYLOAD 0xA0 |
#define | NRF_FLUSH_TX 0xE1 |
#define | NRF_FLUSH_RX 0xE2 |
#define | NRF_REUSE_TX_PL 0xE3 |
#define | NRF_R_RX_PAYLOAD_WID 0x60 |
#define | NRF_W_ACK_PAYLOAD 0xA8 |
#define | NRF_W_TX_PAYLOAD_NOACK 0xB0 |
#define | NRF_NOP 0xFF |
#define | NRF_LOCK_UNLOCK 0x50 |
- Register Memory Map - | |
#define | NRF_CONFIG 0x00 |
#define | NRF_EN_AA 0x01 |
#define | NRF_EN_RXADDR 0x02 |
#define | NRF_SETUP_AW 0x03 |
#define | NRF_SETUP_RETR 0x04 |
#define | NRF_RF_CH 0x05 |
#define | NRF_RF_SETUP 0x06 |
#define | NRF_STATUS 0x07 |
#define | NRF_OBSERVE_TX 0x08 |
#define | NRF_RPD 0x09 |
#define | NRF_RX_ADDR_P0 0x0A |
#define | NRF_RX_ADDR_P1 0x0B |
#define | NRF_RX_ADDR_P2 0x0C |
#define | NRF_RX_ADDR_P3 0x0D |
#define | NRF_RX_ADDR_P4 0x0E |
#define | NRF_RX_ADDR_P5 0x0F |
#define | NRF_TX_ADDR 0x10 |
#define | NRF_RX_PW_P0 0x11 |
#define | NRF_RX_PW_P1 0x12 |
#define | NRF_RX_PW_P2 0x13 |
#define | NRF_RX_PW_P3 0x14 |
#define | NRF_RX_PW_P4 0x15 |
#define | NRF_RX_PW_P5 0x16 |
#define | NRF_FIFO_STATUS 0x17 |
#define | NRF_DYNPD 0x1C |
#define | NRF_FEATURE 0x1D |
CONFIG register bit definitions | |
#define | NRF_CONFIG_MASK_RX_DR 6 |
#define | NRF_CONFIG_MASK_TX_DS 5 |
#define | NRF_CONFIG_MASK_MAX_RT 4 |
#define | NRF_CONFIG_EN_CRC 3 |
#define | NRF_CONFIG_CRCO 2 |
#define | NRF_CONFIG_PWR_UP 1 |
#define | NRF_CONFIG_PRIM_RX 0 |
RF_SETUP register bit definitions | |
#define | NRF_SETUP_PLL_LOCK 4 |
#define | NRF_SETUP_RF_DR 3 |
#define | NRF_SETUP_RF_PWR1 2 |
#define | NRF_SETUP_RF_PWR0 1 |
#define | NRF_SETUP_LNA_HCURR 0 |
STATUS register bit definitions | |
#define | NRF_STATUS_RX_DR 6 |
#define | NRF_STATUS_TX_DS 5 |
#define | NRF_STATUS_MAX_RT 4 |
#define | NRF_STATUS_TX_FULL 0 |
FIFO_STATUS register bit definitions | |
#define | NRF_FIFOSTATUS_TX_REUSE 6 |
#define | NRF_FIFOSTATUS_TX_FIFO_FULL 5 |
#define | NRF_FIFOSTATUS_TX_EMPTY 4 |
#define | NRF_FIFOSTATUS_RX_FULL 1 |
#define | NRF_FIFOSTATUS_RX_EMPTY 0 |
Header file defining register mapping with bit definitions. This file is radio-chip dependent, and are included with the hal_nrf.h
#define NRF_CONFIG 0x00 |
nRF24L01 config register
#define NRF_CONFIG_CRCO 2 |
CONFIG register bit 2
#define NRF_CONFIG_EN_CRC 3 |
CONFIG register bit 3
#define NRF_CONFIG_MASK_MAX_RT 4 |
CONFIG register bit 4
#define NRF_CONFIG_MASK_RX_DR 6 |
CONFIG register bit 6
#define NRF_CONFIG_MASK_TX_DS 5 |
CONFIG register bit 5
#define NRF_CONFIG_PRIM_RX 0 |
CONFIG register bit 0
#define NRF_CONFIG_PWR_UP 1 |
CONFIG register bit 1
#define NRF_DYNPD 0x1C |
nRF24L01 Dynamic payload setup
#define NRF_DYNPD_DPL_P0 0 |
dynamic payload enable
#define NRF_DYNPD_DPL_P1 1 |
dynamic payload enable
#define NRF_DYNPD_DPL_P2 2 |
dynamic payload enable
#define NRF_DYNPD_DPL_P3 3 |
dynamic payload enable
#define NRF_DYNPD_DPL_P4 4 |
dynamic payload enable
#define NRF_DYNPD_DPL_P5 5 |
dynamic payload enable
#define NRF_EN_AA 0x01 |
nRF24L01 enable Auto-Acknowledge register
#define NRF_EN_RXADDR 0x02 |
nRF24L01 enable RX addresses register
#define NRF_ENAA_ENAA_P0 0 |
dynamic payload enable
#define NRF_ENAA_ENAA_P1 1 |
dynamic payload enable
#define NRF_ENAA_ENAA_P2 2 |
dynamic payload enable
#define NRF_ENAA_ENAA_P3 3 |
dynamic payload enable
#define NRF_ENAA_ENAA_P4 4 |
dynamic payload enable
#define NRF_ENAA_ENAA_P5 5 |
dynamic payload enable
#define NRF_FEATURE 0x1D |
nRF24L01 Exclusive feature setup
#define NRF_FEATURE_EN_ACK_PAY 1 |
dynamic payload enable
#define NRF_FEATURE_EN_DPL 2 |
dynamic payload enable
#define NRF_FEATURE_EN_DYN_ACK 0 |
dynamic payload enable
#define NRF_FIFO_STATUS 0x17 |
nRF24L01 FIFO status register
#define NRF_FIFOSTATUS_RX_EMPTY 0 |
FIFO_STATUS register bit 0
#define NRF_FIFOSTATUS_RX_FULL 1 |
FIFO_STATUS register bit 1
#define NRF_FIFOSTATUS_TX_EMPTY 4 |
FIFO_STATUS register bit 4
#define NRF_FIFOSTATUS_TX_FIFO_FULL 5 |
FIFO_STATUS register bit 5
#define NRF_FIFOSTATUS_TX_REUSE 6 |
FIFO_STATUS register bit 6
#define NRF_FLUSH_RX 0xE2 |
Flush RX register command
#define NRF_FLUSH_TX 0xE1 |
Flush TX register command
#define NRF_LOCK_UNLOCK 0x50 |
Lock/unlcok exclusive features
#define NRF_NOP 0xFF |
No Operation command, used for reading status register
#define NRF_OBSERVE_TX 0x08 |
nRF24L01 transmit observe register
#define NRF_R_REGISTER 0x00 |
Register read command
#define NRF_R_RX_PAYLOAD 0x61 |
Read RX payload command
#define NRF_R_RX_PAYLOAD_WID 0x60 |
Read RX payload command
#define NRF_REUSE_TX_PL 0xE3 |
Reuse TX payload command
#define NRF_RF_CH 0x05 |
nRF24L01 RF channel register
#define NRF_RF_SETUP 0x06 |
nRF24L01 RF setup register
#define NRF_RPD 0x09 |
nRF24L01 receive power detect register
#define NRF_RX_ADDR_P0 0x0A |
nRF24L01 receive address data pipe0
#define NRF_RX_ADDR_P1 0x0B |
nRF24L01 receive address data pipe1
#define NRF_RX_ADDR_P2 0x0C |
nRF24L01 receive address data pipe2
#define NRF_RX_ADDR_P3 0x0D |
nRF24L01 receive address data pipe3
#define NRF_RX_ADDR_P4 0x0E |
nRF24L01 receive address data pipe4
#define NRF_RX_ADDR_P5 0x0F |
nRF24L01 receive address data pipe5
#define NRF_RX_PW_P0 0x11 |
nRF24L01 # of bytes in rx payload for pipe0
#define NRF_RX_PW_P1 0x12 |
nRF24L01 # of bytes in rx payload for pipe1
#define NRF_RX_PW_P2 0x13 |
nRF24L01 # of bytes in rx payload for pipe2
#define NRF_RX_PW_P3 0x14 |
nRF24L01 # of bytes in rx payload for pipe3
#define NRF_RX_PW_P4 0x15 |
nRF24L01 # of bytes in rx payload for pipe4
#define NRF_RX_PW_P5 0x16 |
nRF24L01 # of bytes in rx payload for pipe5
#define NRF_SETUP_AW 0x03 |
nRF24L01 setup of address width register
#define NRF_SETUP_LNA_HCURR 0 |
RF_SETUP register bit 0
#define NRF_SETUP_PLL_LOCK 4 |
RF_SETUP register bit 4
#define NRF_SETUP_RETR 0x04 |
nRF24L01 setup of automatic retransmission register
#define NRF_SETUP_RF_DR 3 |
RF_SETUP register bit 3
#define NRF_SETUP_RF_PWR0 1 |
RF_SETUP register bit 1
#define NRF_SETUP_RF_PWR1 2 |
RF_SETUP register bit 2
#define NRF_STATUS 0x07 |
nRF24L01 status register
#define NRF_STATUS_MAX_RT 4 |
STATUS register bit 4
#define NRF_STATUS_RX_DR 6 |
STATUS register bit 6
#define NRF_STATUS_TX_DS 5 |
STATUS register bit 5
#define NRF_STATUS_TX_FULL 0 |
STATUS register bit 0
#define NRF_TX_ADDR 0x10 |
nRF24L01 transmit address
#define NRF_W_ACK_PAYLOAD 0xA8 |
Write ACK payload command
#define NRF_W_REGISTER 0x20 |
Register write command
#define NRF_W_TX_PAYLOAD 0xA0 |
Write TX payload command
#define NRF_W_TX_PAYLOAD_NOACK 0xB0 |
Write ACK payload command