FSM Simulation

Project Description
  • 50 Word Description
  • Functional Description
  • Scoring Algorithm
  • Pin Count
  • Pin Map

    Interactive Floor Plan
  • Old Block Diagrams

    Timing Diagrams
  • FSM Timing Diagram
  • Input Timing Diagram
  • Logic Timing Diagram
  • Output Timing Diagram

    FSM Design and MEG
  • FSM State Table
  • FSM Inputs and Outputs
  • FSM Magic Layout
  • FSM IRSIM

    Major Blocks & Subcells
  • Logic Diagram Links
  • Cell Hierarchy
  • Magic and IRSIM

    Performance Analysis
  • IRSIM
  • Spice

    Summary

    About Us
  • Mid-Semester Status Report
  • FSM Sim. 1

    Command File

    |this wins on second guess
    stepsize 100
    vector STATE SB0 SB1 SB2 SB3
    ana clka clkb STATE RESTART enterK enterG S2 S1 S0 GC2 GC1 GC0 latchK resetBW latchG shift0 shift1 shift2 shift3 latchGBS resetV latchVBS WLK1 WLK0 latchGC resetGC incrementGC latchLS latchB latchW resetO latchO latchC

    clock clka 0 1 0 0
    clock clkb 0 0 0 1
    | a b c d e f g h i b c d e f k a
    V RESTART 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
    V S2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
    V S1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
    V S0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
    V enterG 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
    V enterK 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
    V GC2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
    V GC1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
    V GC0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0

    R

    Results in PostScript form


    FSM Sim. 2

    |force running out of guesses after 3rd guess
    stepsize 100
    vector STATE SB0 SB1 SB2 SB3
    ana clka clkb STATE RESTART enterK enterG S2 S1 S0 GC2 GC1 GC0 latchK resetBW latchG shift0 shift1 shift2 shift3 latchGBS resetV latchVBS WLK1 WLK0 latchGC resetGC incrementGC latchLS latchB latchW resetO latchO latchC

    clock clka 0 1 0 0
    clock clkb 0 0 0 1
    | a b c d e f g h i b c d e f g h i b c d e f g h i j a
    V RESTART 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
    V S2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
    V S1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
    V S0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
    V enterG 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
    V enterK 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
    V GC2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
    V GC1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1
    V GC0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1

    R

    Results in PostScript form


    Last modified: Sat Oct 30 21:37:15 CDT 1999